Datasheet

Data Sheet AD9888
Rev. C | Page 23 of 36
Hex
Address
Read and
Write, or
Read Only Bits
Default
Value Register Name Function
0x15
R/W
[7:0] 1*******
Bit 7—channel mode. Determines single-channel or dual-channel output
mode. Logic 0 = single-channel mode; Logic 1 = dual-channel mode.
*1******
Bit 6—output mode. Determines interleaved or parallel output mode.
Logic 0 = interleaved mode; Logic 1 = parallel mode.
**0*****
Bit 5—A/B invert control. Determines which port outputs the first data
byte after HSYNC. Logic 0 = A port; Logic 1 = B port.
***0****
Bit 4—4:2:2 output formatting mode select. Logic 0 = 4:4:4 output format-
ting mode; Logic 1 = 4:2:2 output formatting mode.
****0***
Bit 3—input mux control. Logic 0 = Channel 0 selected; Logic 1 = Channel 1
selected
*****11*
Bits [2:1]—analog bandwidth control. Logic 00 = 75 MHz; Logic 01 =
150 MHz; Logic 10 = 300 MHz; Logic 11 = 500 MHz.
*******0
Bit 0—external clock select. Shuts down PLL and allows external clock
to drive the part. Logic 0 = use internal PLL; Logic 1 = bypassing of the
internal PLL.
0x16
R/W
[7:0] 11111111 Test register Must be set to 11111110 for proper operation.
0x17
R/W
[7:3] 00000000 Test register Must be set to default for proper operation.
0x18 RO [7:0] Test register
0x19 RO [7:0] Test register
1
The AD9888 updates the PLL divide ratio only when the LSBs of the PLL divider are written to in Register 0x02.