Datasheet

AD9888 Data Sheet
Rev. C | Page 14 of 36
GAIN
0x FF 0x 00
INPUT RANGE (V)
1.0
0.5
0
OFFSET = 0x00
OFFSET = 0x3F
OFFSET = 0x7F
OFFSET = 0x00
OFFSET = 0x7F
OFFSET = 0x3F
02442-004
Figure 5. Gain and Offset Control
SYNC-ON-GREEN INPUT
The sync-on-green input operates in two steps. First, with the
aid of a negative peak detector, it sets a baseline clamp level from
the incoming video signal. Second, it sets the threshold level
(nominally 150 mV above the negative peak). The exact threshold
level is variable and can be programmed via Register 0x10. The
sync-on-green input must be ac-coupled to the green analog
input through its own capacitor, as shown in Figure 6. The value
of the capacitor must be 1 nF ± 20%. If sync-on-green input is
not used, this connection is not required and the SOGIN pin
should be left unconnected. (Note that the sync-on-green signal
is always negative polarity.) For more details, see the Sync
Processing Overview section.
G
AIN[1:0]
SOGINx
1nF
R
AIN[1:0]
47n
F
B
AIN[1:0]
47nF
47nF
02442-005
Figure 6. Typical Clamp Configuration for RGB/YUV Applications
CLOCK GENERATION
A PLL is employed to generate the pixel clock. The HSYNC
input provides a reference frequency to the PLL. A voltage
controlled oscillator (VCO) generates a much higher pixel clock
frequency. This pixel clock is divided by the PLL divide value
(Register 0x01 and Register 0x02), and the phase is compared
with the HSYNC input. Any error is used to shift the VCO
frequency and maintain lock between the two signals.
The stability of this clock is very important for providing the
clearest and most stable image. During each pixel time, there is
a period during which the signal is slewing from the old pixel
amplitude and settling to a new value. Then, the input voltage is
stable until the signal slews to a new value (see Figure 7). The
ratio of the slewing time to the stable time is a function of the
bandwidth of the graphics DAC, the bandwidth of the trans-
mission system (cable and termination), and the overall pixel
rate. Therefore, if the dynamic characteristics of the system
remain fixed, the slewing and settling times are likewise fixed.
These times must be subtracted from the total pixel period to
determine the stable period. At higher pixel frequencies, both
the total cycle time and stable pixel time are shorter.
PIXEL CLOCK
INVALID SAMPLE TIMES
02442-006
Figure 7. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must be subtracted from
the stable pixel time. The AD9888 clock generation circuit is
designed to minimize jitter to less than 9% of the total pixel
time in all operating modes, making its effect on valid sampling
time negligible (see Figure 8).
02442-007
PIXEL CLOCK (MHz)
25.2 31.5 31.5 36.0 36.0 50.0 40.0 49.5 56.3 65.0 75.0 78.8 85.5 94.5
108.0 135.0 160.0 162.0 170.0
JITTER PEAK-TO-PEAK (%)
14
12
10
8
6
4
2
0
Figure 8. Pixel Clock Jitter vs. Frequency
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is illustrated in Figure 9.
Recommended settings of VCO range and charge pump current
for VESA standard display modes are listed in Table 5.
C
P
0
.0039µF
C
Z
0.039µF
R
Z
3.3kΩ
FILT
PV
D
02442-008
Figure 9. PLL Loop Filter Detail