Datasheet

REV. 0
–24–
AD9887
GENERAL TIMING DIAGRAMS (DIGITAL INTERFACE)
80%
80%
20%
20%
D
LHT
D
LHT
Figure 28. Digital Output Rise and Fall Time
T
CIH
, R
CIH
T
CIP
, R
CIP
T
CIL
, R
CIL
Figure 29. Clock Cycle/High/Low Times
V
DIFF
= 0V
T
CCS
V
DIFF
= 0V
R
X0
R
X1
R
X2
Figure 30. Channel-to-Channel Skew Timing
DATACK
(INTERNAL)
DATACK
(PIN)
t
SKEW
DATA OUT
Figure 31. DVI Output Timing
TIMING MODE DIAGRAMS (DIGITAL INTERFACE)
FIRST
PIXEL
SECOND
PIXEL
THIRD
PIXEL
FOURTH
PIXEL
INTERNAL
ODCLK
DATACK
DE
QE[23:0]
QO[23:0]
T
ST
Figure 32. 1 Pixel per Clock (DATACK Inverted)
FIRST
PIXEL
SECOND
PIXEL
THIRD
PIXEL
FOURTH
PIXEL
INTERNAL
ODCLK
DATACK
DE
QE[23:0]
QO[23:0]
T
ST
Figure 33. 1 Pixels per Clock (DATACK Inverted)
FIRST PIXEL
SECOND PIXEL
THIRD PIXEL
FOURTH PIXEL
INTERNAL
ODCLK
DATACK
DE
QE[23:0]
QO[23:0]
T
ST
Figure 34. 2 Pixel per Clock
FIRST PIXEL
SECOND PIXEL
THIRD PIXEL
FOURTH PIXEL
INTERNAL
ODCLK
DATACK
DE
QE[23:0]
QO[23:0]
T
ST
Figure 35. 2 Pixels per Clock (DATACK Inverted)
OBSOLETE