Datasheet

REV. 0
–22–
AD9887
6-PIPE DELAY
P0 P1 P2 P3 P4 P5 P6 P7
U0 V2 U4 V4 U6
RGBIN
HSYNC
PXCK
HS
ADCCK
DATACK
ROUTA
HSOUT
Y0 Y1 Y2 Y3 Y4 Y5 Y6
GOUTA
V0 U2 V6
Figure 27. 4:2:2 Output Mode
Table VIII. Digital Interface Pin List
Pin Type Pin Name Function Value Pin No.
Digital Video Data Inputs Rx0+ Digital Input Channel 0 True 62
Rx0– Digital Input Channel 0 Complement 63
Rx1+ Digital Input Channel 1 True 59
Rx1– Digital Input Channel 1 Complement 60
Rx2+ Digital Input Channel 2 True 56
Rx2– Digital Input Channel Two’s Complement 57
Digital Video Clock Inputs RxC+ Digital Data Clock True 65
RxC– Digital Data Clock Complement 66
Termination Control R
TERM
Control Pin for Setting the Internal 53
Termination Resistance
Outputs DE Data Enable 3.3 V CMOS 137
HSYNC HSYNC Output 3.3 V CMOS 139
VSYNC VSYNC Output 3.3 V CMOS 138
CTL0, CTL1, Decoded Control Bit Outputs 3.3 V CMOS 46–49
CTL2, CTL3
Power Supply V
D
Main Power Supply 3.3 V ± 5%
PV
D
PLL Power Supply 3.3 V ± 5%
V
DD
Output Power Supply 3.3 V or 2.5 V ± 5%
GND Ground Supply 0 V
GND Ground Supply 0 V
OBSOLETE