Datasheet

REV. 0
AD9887
–21–
5-PIPE DELAY
D1 D5
D3 D7
P0 P1 P2 P3 P4 P5 P6 P7
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
HSOUT
D
OUTB
Figure 24. Dual Channel Mode, Interleaved Outputs, 2 Pixels/Clock (Odd Pixels) (Analog Interface), Outphase = 1
7-PIPE DELAY
P0 P1 P2 P3 P4 P5 P6 P7
D0 D4
D2 D6
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
D
OUTB
HSOUT
Figure 25. Dual Channel Mode, Parallel Outputs, 2 Pixels/Clock (Even Pixels) (Analog Interface), Outphase = 1
7.5-PIPE DELAY
P0 P1 P2 P3 P4 P5 P6 P7
D1 D5
D3 D7
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
D
OUTB
HSOUT
Figure 26. Dual Channel Mode, Parallel Outputs, 2 Pixels/Clock (Odd Pixels) (Analog Interface), Outphase = 1
OBSOLETE