Datasheet

REV. 0
–20–
AD9887
P0 P1 P2 P3 P4 P5 P6 P7
3-PIPE DELAY
D0 D2 D4 D6
D1 D3 D5
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
HSOUT
D
OUTB
D7
Figure 21. Dual Channel Mode, Interleaved Outputs (Analog Interface), Outphase = 1
P0 P1 P2 P3 P4 P5 P6 P7
7-PIPE DELAY
D0
D2 D4 D6
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
HSOUT
D
OUTB
D1
D3 D5 D7
Figure 22. Dual Channel Mode, Parallel Outputs (Analog Interface), Outphase = 1
3-PIPE DELAY
P0 P1 P2 P3 P4 P5 P6 P7
D4
D2 D6
RGB
IN
HSYNC
PxCK
HS
ADCCK
DATACK
D
OUTA
HSOUT
D
OUTB
D0
Figure 23. Dual Channel Mode, Interleaved Outputs, 2 Pixels/Clock (Even Pixels) (Analog Interface), Outphase = 1
OBSOLETE