Datasheet

AD9880
Rev. 0 | Page 8 of 64
Pin Type Pin No. Mnemonic Function Value
OUTPUTS 92 to 99 RED [7:0] Outputs of Red Converter, Bit 7 is MSB V
DD
2 to 9 GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB V
DD
12 to 19 BLUE [7:0] Outputs of Blue Converter, Bit 7 is MSB V
DD
89 DATACK Data Output Clock V
DD
87 HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) V
DD
85 VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) V
DD
86 SOGOUT SOG Slicer Output V
DD
84 O/E FIELD Odd/Even Field Output V
DD
REFERENCES 57 FILT Connection For External Filter Components For PLL
POWER SUPPLY
80, 76, 72,
67, 45, 33
V
D
Analog Power Supply and DVI Terminators 3.3 V
100, 90, 10 V
DD
Output Power Supply 1.8 V to 3.3 V
59, 56, 54 PV
DD
PLL Power Supply 1.8 V
48, 32, 30 DV
DD
Digital Logic Power Supply 1.8 V
GND Ground 0 V
CONTROL 83 SDA Serial Port Data I/O 3.3 V CMOS
82 SCL Serial Port Data Clock 3.3 V CMOS
HDCP 49 DDC_SCL HDCP Slave Serial Port Data Clock 3.3 V CMOS
50 DDC_SDA HDCP Slave Serial Port Data I/O 3.3 V CMOS
51 MCL HDCP Master Serial Port Data Clock 3.3 V CMOS
52 MDA HDCP Master Serial Port Data I/O 3.3 V CMOS
AUDIO DATA OUTPUTS 28 S/PDIF S/PDIF Digital Audio Output V
DD
27 I2S0 I
2
S Audio (Channels 1, 2) V
DD
26 I2S1 I
2
S Audio (Channels 3, 4) V
DD
25 I2S2 I
2
S Audio (Channels 5, 6) V
DD
24 I2S3 I
2
S Audio (Channels 7, 8) V
DD
20 MCLKIN External Reference Audio Clock In V
DD
21 MCLKOUT Audio Master Clock Output V
DD
22 SCLK Audio Serial Clock Output V
DD
23 LRCLK Data Output Clock For Left And Right Audio Channels V
DD
DIGITAL VIDEO DATA 35 Rx0+ Digital Input Channel 0 True TMDS
34 Rx0− Digital Input Channel 0 Complement TMDS
38 Rx1+ Digital Input Channel 1 True TMDS
37 Rx1− Digital Input Channel 1 Complement TMDS
41 Rx2+ Digital Input Channel 2 True TMDS
40 Rx2− Digital Input Channel 2 Complement TMDS
DIGITAL VIDEO CLOCK INPUTS 43 RxC+ Digital Data Clock True TMDS
44 RxC− Digital Data Clock Complement TMDS
DATA ENABLE 88 DE Data Enable 3.3 V CMOS
RTERM 46 RTERM Sets Internal Termination Resistance
500Ω