Datasheet

AD9880
Rev. 0 | Page 55 of 64
Table 96.
ISRC1 Valid Description
0 ISRC1 status bits and PBs not valid
1 ISRC1 status bits and PBs valid
0xC8 2-0 ISRC Status
These bits define where in the ISRC track the samples
are: at least two transmissions of 001 occur at the
beginning of the track, while in the middle of the
track, continuous transmission of 010 occurs followed
by at least two transmissions of 100 near the end of the
track.
0xC9 7-0 ISRC1 Packet Byte 0 (ISRC1_PB0)
0xCA 7-0 ISRC1_PB1
0xCB 7-0 ISRC1_PB2
0xCC 7-0 ISRC1_PB3
0xCD 7-0 ISRC1_PB4
0xCE 7-0 ISRC1_PB5
0xCF 6-0 New Data Flags
See Register 0x87 for a description.
0xD0 7-0 ISRC1_PB6
0xD1 7-0 ISRC1_PB7
0xD2 7-0 ISRC1_PB8
0xD3 7-0 ISRC1_PB9
0xD4 7-0 ISRC1_PB10
0xD5 7-0 ISRC1_PB11
0xD6 7-0 ISRC1_PB12
0xD7 6-0 New Data Flags
See Register 0x87 for a description.
0xD8 7-0 ISRC1_PB13
0xD9 7-0 ISRC1_PB14
0xDA 7-0 ISRC1_PB15
0xDB 7-0 ISRC1_PB16
0xDC 7-0 ISRC2 Packet Byte 0 (ISRC2_PB0)
This is transmitted only when the ISRC continue bit
(Register 0xC8 Bit 7) is set to 1.
0xDD 7-0 ISRC2_PB1
0xDE 7-0 ISRC2_PB2
0xDF 6-0 New Data Flags
See Register 0x87 for a description.
0xE0 7-0 ISRC2_PB3
0xE1 7-0 ISRC2_PB4
0xE2 7-0 ISRC2_PB5
0xE3 7-0 ISRC2_PB6
0xE4 7-0 ISRC2_PB7
0xE5 7-0 ISRC2_PB8
0xE6 7-0 ISRC2_PB9
0xE7 6-0 New Data Flags
See Register 0x87 for a description.
0xE8 7-0 ISRC2_PB10
0xE9 7-0 ISRC2_PB11
0xEA 7-0 ISRC2_PB12
0xEB 7-0 ISRC2_PB13
0xEC 7-0 ISRC2_PB14
0xED 7-0 ISRC2_PB15
0xEE 7-0 ISRC2_PB16