Analog/HDMI Dual Display Interface AD9880 FEATURES FUNCTIONAL BLOCK DIAGRAM ANALOG INTERFACE R/G/B OR YPbPrIN1 2:1 MUX HSYNC 0 HSYNC 1 HSYNC 0 HSYNC 1 2:1 MUX SOGIN 0 SOGIN 1 2:1 MUX COAST FILT CKINV CKEXT 2:1 MUX R/G/B 8X3 A/D CLAMP SYNC PROCESSING AND CLOCK GENERATION or YCbCr 2 DATACK HSOUT VSOUT SOGOUT REFOUT REFIN REF SCL SERIAL REGISTER AND POWER MANAGEMENT R/G/B 8X3 YCbCr (4:2:2 OR 4:4:4) 2 RGB SDA YCbCr MATRIX R/G/B OR YPbPrIN0 MUXES DATACK HSOUT VSOUT SOGOUT DIGITAL INTERFAC
AD9880 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Diagrams ....................................................................... 21 Analog Interface Electrical Characteristics............................... 3 2-Wire Serial Register Map ........................................................... 23 Digital Interface Electrical Characteristics ............................... 4 2-Wire Serial Control Register Detail......
AD9880 SPECIFICATIONS ANALOG INTERFACE ELECTRICAL CHARACTERISTICS VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum. Table 1. Temp Test Level 25°C I Integral Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Full-Scale Matching 25°C Full I Full Full +25°C +25°C 25C Full Full VI VI V V VI VI V Full Full Full VI VI IV Full Full Full Full Full Full Full Full Full Full Full +25°C Full VI VI VI VI VI VI VI VI VI VI IV IV IV 4.
AD9880 Parameter VDD Supply Voltage PVDD Supply Voltage ID Supply Current (VD) IDVDD Supply Current (DVDD) IDD Supply Current (VDD) 2 IPVDD Supply Current (PVDD) Total Power Power-Down Dissipation DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Signal–to–Noise Ratio (SNR) Without Harmonics fIN = 40.7 MHz Crosstalk THERMAL CHARACTERISTICS θJA-Junction-to-Ambient 1 2 3 Min 1.7 1.7 AD9880KSTZ-100 Typ Max 3.3 3.47 1.8 1.9 260 300 45 60 37 100 3 10 15 1.1 1.4 130 Min 1.7 1.7 AD9880KSTZ-150 Typ Max 3.3 3.
AD9880 AD9880KSTZ-100 Parameter POWER SUPPLY VD Supply Voltage VDD Supply Voltage DVDD Supply Voltage PVDD Supply Voltage IVD Supply Current (Typical Pattern) 1 IVDD Supply Current (Typical Pattern) 2 IDVDD Supply Current (Typical Pattern)1, 4 IPVDD Supply Current (Typical Pattern)1 Power-Down Supply Current (IPD) AC SPECIFICATIONS Intrapair (+ to −) Differential Input Skew (TDPS) Channel to Channel Differential Input Skew (TCCS) Low-to-High Transition Time for Data and Controls (DLHT) Test Level IV IV IV
AD9880 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VD VDD DVDD PVDD Analog Inputs Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature EXPLANATION OF TEST LEVELS Rating 3.6 V 3.6 V 1.98 V 1.98 V VD to 0.0 V 5 V to 0.0 V 20 mA −25°C to + 85°C −65°C to + 150°C 150°C 150°C Test Level I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV.
AD9880 75 GND 74 GAIN0 RED 0 RED 1 RED 2 RED 3 RED 4 RED 5 RED 6 RED 7 GND VDD DATACLK DE HSOUT SOGOUT VSOUT O/E FIELD SDA SCL PWRDN VD RAIN0 GND RAIN1 VD 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND 1 GREEN 7 2 GREEN 6 3 73 SOGIN0 GREEN 5 4 72 VD GAIN1 PIN 1 GREEN 4 5 71 GREEN 3 6 70 SOGIN1 GREEN 2 7 69 GND BAIN0 GREEN 1 8 68 GREEN 0 9 67 VD VDD 10 AD9880 66 BAIN1 TOP VIEW (Not to Scale)
AD9880 Pin Type OUTPUTS REFERENCES POWER SUPPLY CONTROL HDCP AUDIO DATA OUTPUTS DIGITAL VIDEO DATA DIGITAL VIDEO CLOCK INPUTS DATA ENABLE RTERM Pin No.
AD9880 Table 5. Pin Function Descriptions Pin INPUTS RAIN0 GAIN0 BAIN0 RAIN1 GAIN1 BAIN1 B B Rx0+ Rx0− Rx1+ Rx1− Rx2+ Rx2− RxC+ RxC− HSYNC0 HSYNC1 VSYNC0 VSYNC1 SOGIN0 SOGIN1 EXTCLK/COAST EXTCLK/COAST Description Analog Input for the Red Channel 0. Analog Input for the Green Channel 0. Analog Input for the Blue Channel 0. Analog Input for the Red Channel 1. Analog Input for the Green Channel 1. Analog Input for Blue Channel 1.
AD9880 Pin PWRDN FILT OUTPUTS HSOUT VSOUT SOGOUT O/E FIELD SERIAL PORT SDA SCL DDCSDA DDCSCL MDA MCL DATA OUTPUTS Red [7:0] Green [7:0] Blue [7:0] DATA CLOCK OUTPUT DATACK Description Power-Down Control/Three-State Control. The function of this pin is programmable via Register 0x26 [2:1]. External Filter Connection. For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin.
AD9880 Pin POWER SUPPLY 1 VD (3.3 V) VDD (1.8 V – 3.3 V) PVDD (1.8 V) DVDD (1.8 V) GND 1 Description Analog Power Supply. These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible. Digital Output Power Supply. A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply transients (noise).
AD9880 DESIGN GUIDE The AD9880 is a fully integrated solution for capturing analog RGB or YUV signals and digitizing them for display on flat panel monitors, projectors, or PDPs. In addition, the AD9880 has a digital interface for receiving DVI/HDMI signals and is capable of decoding HDCP encrypted signals through connections to an internal EEPROM. The circuit is ideal for providing an interface for HDTV monitors or as the front end to high performance video scan converters.
AD9880 This introduces a 700 mV dc offset to the signal, which must be removed for proper capture by the AD9880. within ½ LSB in 10 lines with a clamp duration of 20 pixel periods on a 75 Hz SXGA signal. The key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. An offset is then introduced which results in the ADCs producing a black output (Code 0x00) when the known black input is present.
AD9880 required. Note that the SOG signal is always negative polarity. For additional detail on setting the SOG threshold and other SOG-related functions, see the Sync Processing section. 47nF RAIN The PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is illustrated in Figure 6. Recommended settings of the VCO range and charge pump current for VESA standard display modes are listed in Table 8.
AD9880 Power Management The AD9880 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: full-power, seek mode, auto power-down and power-down. Table 7 summarizes how the AD9880 determines which power mode to be in and which circuitry is powered on/off in each of these modes.
AD9880 TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the AD9880, which must be flushed before valid data becomes available. This means 23 data sets are presented before valid data is available. The timing diagram in Figure 7 shows the operation of the AD9880. tPER The Coast input is provided to eliminate this problem.
AD9880 Sync Slicer signal is routed to a comparator with a variable trigger level (set by Register 0x1D, Bits [7:3]), but nominally 0.128 V above the clamped voltage. The sync slicer output is a digital composite sync signal containing both Hsync and Vsync information (see Figure 9). The purpose of the sync slicer is to extract the sync signal from the green graphics or luminance video signal that is connected to the SOGIN input. The sync signal is extracted in a two step process.
AD9880 Sync Separator As part of sync processing, the sync separator’s task is to extract Vsync from the composite sync signal. It works on the idea that the Vsync signal stays active for a much longer time than the Hsync signal. By using a digital low-pass filter and a digital comparator, it rejects pulses with small durations (such as Hsyncs and equalization pulses) and only passes pulses with large durations, such as Vsync (see Figure 9).
AD9880 HSYNCIN FILTER WINDOW HSYNCOUT VSYNC EQUALIZATION PULSES EXPECTED EDGE 05087-010 FILTER WINDOW Figure 10. Sync Processing Filter Vsync Filter and Odd/Even Fields SYNC SEPARATOR THRESHOLD The Vsync filter is used to eliminate spurious Vsyncs, maintain a consistent timing relationship between the Vsync and Hsync output signals, and generate the odd/even field output.
AD9880 HDMI RECEIVER Output modes supported are The HDMI receiver section of the AD9880 allows the reception of a digital video stream, which is backward-compatible with DVI and able to accommodate not only video of various formats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of audio. Infoframes are transmitted carrying information about the video format, audio clocks, and many other items necessary for a monitor to utilize fully the information stream available.
AD9880 A programming example and register settings for several common conversions are listed in the Color Space Converter (CSC) Common Settings. • Speaker placement • N and CTS values (for reconstruction of the audio) For a detailed functional description and more programming examples, please refer to the application note AN-795, AD9880 Color space Converter User's Guide.
AD9880 DATAIN P0 P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11 HSIN DATACLK 8 CLOCK CYCLE DELAY DATAOUT P0 P1 P2 P3 05087-015 2 CLOCK CYCLE DELAY HSOUT Figure 15. RGB ADC Timing DATAIN P0 P1 P2 P3 P4 P5 P6 P7 P9 P8 P10 P11 HSIN DATACLK 8 CLOCK CYCLE DELAY YOUT CB/CROUT Y0 Y1 Y2 Y3 B0 R0 B2 R2 2 CLOCK CYCLE DELAY 05087-016 HSOUT 1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT. 2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT. Figure 16. YCrCb ADC Timing Table 10.
AD9880 2-WIRE SERIAL REGISTER MAP The AD9880 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 11.
AD9880 Hex Address 0x12 0x13 0x14 0x15 0x16 Read/Write or Read Only Read/Write Read/Write Read/Write Read Read Bits [7] Default Value 1******* [6] *0****** Hsync Polarity Override [5] **1***** Input Vsync Polarity [4] ***0**** Vsync Polarity Override [3] ****1*** Input Coast Polarity [2] *****0** Coast Polarity Override [1] ******0* Coast Source [0] *******1 Filter Coast Vsync [7:0] [7:0] [7] 00000000 00000000 0******* Precoast Postcoast Hsync 0 Detected [6] *0****** Hsync
AD9880 Hex Address 0x17 Read/Write or Read Only Read Bits [3:0] Default Value ****0000 0x18 0x19 Read Read/Write [7:0] [7:0] 00000000 00001000 Register Name Hsyncs Per Vsync MSB Hsyncs Per Vsync Clamp Placement 0x1A 0x1B Read/Write Read/Write [7:0] [7] 00010100 0******* Clamp Duration Red Clamp Select [6] *0****** Green Clamp Select [5] **0***** Blue Clamp Select [4] ***0**** Clamp During Coast Enable [3] ****0*** Clamp Disable [1] ******1* Programmable Bandwidth [0] *******0
AD9880 Hex Address Read/Write or Read Only Bits [6] Default Value *1****** Register Name PLL Sync Filter Enable [5] **0***** Vsync Filter Enable [4] ***0**** [3] **** 1*** Vsync Duration Enable Auto Offset Clamp Mode [2] **** *1** Auto Offset Clamp Length 0x22 0x23 Read/Write Read/Write [7:0] [7:0] 4 32 Vsync Duration Hsync Duration 0x24 Read/Write [7] 1******* Hsync Output Polarity [6] *1****** Vsync Output Polarity [5] **1***** DE Output Polarity [4] ***1**** Field Output
AD9880 Hex Address 0x26 Read/Write or Read Only Read/Write Bits Default Value [1] ******1* [0] *******0 [7] [6] [5] [4] [3] 0******* *0****** **0***** ***0**** ****1*** [2:1] *****00* Register Name Primary Output Enable Secondary Output Enable Output Three-State SOG Three-State SPDIF Three-State I2S Three-State Power-Down Pin Polarity Power-Down Pin Function [0] *******0 Power-Down [7] 1******* Auto Power-Down Enable [6] *0****** HDCP A0 [5] **0***** MCLK External Enable [4] ***
AD9880 Hex Address 0x2F Read/Write or Read Only Read 0x30 Read Bits [6] [5] [4] [3] [2:0] [6] Default Value *0****** **0***** ***0**** ****0*** *****000 *0****** [5] [4] [3:0] **0***** ***0**** ****0000 DVI Hsync Polarity DVI Vsync Polarity HDMI Pixel Repetition Register Name TMDS Sync Detect TMDS Active AV Mute HDCP Keys Read HDMI Quality HDMI Content Encrypted 0x31 Read/Write [7:4] 1001**** MV Pulse Max 0x32 Read/Write [3:0] [7] ****0110 0******* MV Pulse Min MV Oversample En Read/Writ
AD9880 Hex Address 0x39 0x3A Read/Write or Read Only Read/Write Read/Write Bits [4:0] [7:0] Default Value ***00000 00000000 Register Name CSC_Coeff_A3 MSB CSC_Coeff_A3 0x3B 0x3C Read/Write Read/Write [4:0] [7:0] ***11001 11010111 CSC_Coeff_A4 MSB CSC_Coeff_A4 0x3D 0x3E Read/Write Read/Write [4:0] [7:0] ***11100 01010100 CSC_Coeff_B1 MSB CSC_Coeff_B1 0x3F 0x40 Read/Write Read/Write [4:0] [7:0] ***01000 00000000 CSC_Coeff_B2 MSB CSC_Coeff_B2 0x41 0x42 Read/Write Read/Write [4:0] [7:0] *
AD9880 Hex Address 0x50 0x56 0x57 Read/Write or Read Only Read/Write Read/Write Read/Write 0x58 Read/Write Bits [7:0] [7:0] [7] [6] [3] [2] [7] [6:4] Default Value 00100000 00001111 0******* *0****** ****0*** *****0** Register Name Test Test A/V Mute Override AV Mute Value Disable Video Mute Disable Audio Mute MCLK PLL Enable MCLK PLL_N [3] N_CTS_Disable [2:0] MCLK FS_N MDA/MCL PU CLK Term O/R Manual CLK Term FIFO Reset UF FIFO Reset OF MDA/MCL ThreeState Packet Detected 0x59 Read/Write [6] [5]
AD9880 Hex Address Read/Write or Read Only Bits 0x62 Read [3:0] Word Length 0x7B Read [7:0] CTS [19:12] 0x7C 0x7D Read Read Read [7:0] [7:4] [3:0] CTS [11:4] CTS [3:0] N [19:16] 0x7E 0x7F Read Read [7:0] [7:0] N [15:8] N [7:0] 0x80 0x81 Read Read [7:0] [6:5] 4 [3:2] [1:0] 0x82 Read [7:6] [5:4] Default Value Register Name Frequency Description 0000 = 44.1 kHz. 1000 = 88.2 kHz. 1100 = 176.4 kHz. 0010 = 48k Hz. 1010 = 96 kHz. 1110 = 192 kHz. Word length. 0000 not specified.
AD9880 Hex Address Read/Write or Read Only Bits [3:0] 0x83 Read [1:0] Default Value Register Name Active Format Aspect Ratio Nonuniform Picture Scaling 0x84 Read [6:0] 0x85 Read [3:0] Video Identification Code Pixel Repeat 0x86 Read [7:0] Active Line Start LSB 0x87 Read [6:0] New Data Flags 0x88 0x89 Read Read [7:0] [7:0] Active Line Start MSB Active Line End LSB 0x8A 0x8B Read Read [7:0] [7:0] Active Line End MSB Active Pixel Start LSB 0x8C 0x8D Read Read [7:0] [7:0] Ac
AD9880 Hex Address 0x90 Read/Write or Read Only Read Bits [7:0] 0x91 Read [7:4] [2:0] 0x92 Read [4:2] [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 7 0x95 Read [6:3] 0x96 0x97 Read Read [7:0] [6:0] 0x98 Read [7:0] 0x99 Read [7:0] Default Value Register Name Audio Infoframe Version Audio Coding Type Description CT [3:0]. Audio coding type. 0x00 = Refer to stream header. 0x01 = IEC60958 PCM. 0x02 = AC3. 0x03 = MPEG1 (Layers 1 and 2). 0x04 = MP3 (MPEG1 Layer 3).
AD9880 Hex Address 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 Read/Write or Read Only Read Read Read Read Read Read Read Read Read Bits [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0xB7 Read [6:0] 0xB8 R
AD9880 Hex Address 0xBD Read/Write or Read Only Read Bits [1:0] Default Value 0xBE 0xBF 0xC0 Read Read Read [7:0] [6:0] [7:0] 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 Read Read Read Read Rea Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] 7 ACP Packet Byte 0 ACP_PB1 ACP_PB2 ACP_PB3 ACP_PB4 ACP_PB5 NDF ISRC1 Continued Read 6 ISRC1 Valid [2:0] ISRC1 Status Register Name MPEG Frame New Data Flags Audio Content Protection Packet (ACP) Type 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0
AD9880 Hex Address 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE Read/Write or Read Only Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Default Value Register Name ISRC2_PB3 ISRC2_PB4 ISRC2_PB5 ISRC2_PB6 ISRC2_PB7 ISRC2_PB8 ISRC2_PB9 New Data Flags ISRC2_PB10 ISRC2_PB11 ISRC2_PB12 ISRC2_PB13 ISRC2_PB14 ISRC2_PB15 ISRC2_PB16 Description ISRC2_PB3.
AD9880 2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION CLOCK GENERATOR CONTROL 0x00 0x03 7-0 Chip Revision An 8-bit value that reflects the current chip revision. 7-0 PLL Divide Ratio MSBs The eight most significant bits of the 12-bit PLL divide ratio PLLDIV. The PLL derives a pixel clock from the incoming Hsync signal. The pixel clock frequency is then divided by an integer value, such that the output is phase-locked to Hsync.
AD9880 0x04 7-3 Phase Adjust 0x09 These bits provide a phase adjustment for the DLL to generate the ADC clock. A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift in sampling phase. The power up default is 16. 7-0 0x06 7-0 7-0 0x0A 0x0B Blue Channel Gain Red Channel Offset Adjust If clamp feedback is enabled, the 8-bit offset adjust determines the clamp code.
AD9880 0x0D 7-0 Blue Channel Offset 0x11 These eight bits are the blue channel offset control. The offset control shifts the analog input, resulting in a change in brightness. Note that the function of the offset register depends on whether clamp feedback is enabled (Register 0x1C, Bit 7 = 1). If clamp feedback is disabled, the offset register bits control the absolute offset added to the channel.
AD9880 0x13 7-0 Precoast Table 17. Vsync0 Detection Results This register allows the internally generated Coast signal to be applied prior to the Vsync signal. This is necessary in cases where pre-equalization pulses are present. The step size for this control is one Hsync period. For Precoast to work correctly, it is necessary for the Vsync filter (0x21, Bit 5) and sync processing filter (0x21 Bit 7) both to be either enabled or disabled. The power-up default is 0.
AD9880 0x15 1 Table 27. Sync Filter Lock Detect Coast Detection Bit This bit detects activity on the EXTCLK/EXTCOAST pin. It indicates that one of the two signals is active, but it doesn’t indicate if it is EXTCLK or EXTCOAST. A dc signal is not detected. Table 21. Coast Detection Results Detect 0 1 Detect 0 1 0x16 0x17 7 0x18 Hsync0 Polarity Table 22.
AD9880 0x1B 5 Blue Clamp Select 0x1C This bit selects whether the blue channel is clamped to ground or midscale. Ground clamping is used for blue in RGB applications and midscale clamping is used in YPrPb (YUV) applications. Result Channel clamped to ground during clamping period Channel clamped to midscale during clamping period 0x1C 4 Clamp During Coast This bit permits clamping to be disabled during Coast.
AD9880 0x20 7-0 Sync Filter Window Width predictable relative position between Hsync and Vsync edges at the output. This 8-bit register sets the distance in 40 MHz clock periods (25 ns), which is the allowed distance for Hsync pulses before and after the expected Hsync edge. This is the heart of the filter in that it only looks for Hsync pulses at a given time (plus or minus this window) and then ignores extraneous equalization pulses that disrupt accurate PLL operation.
AD9880 0x23 7-0 Hsync Duration 0x24 An 8 bit register that sets the duration of the Hsync output pulse. The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9880 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase-adjusted. The power-up default is 32. 0x24 7 Table 45.
AD9880 0x25 Table 48. Output Clock Select Select 00 01 10 11 0x25 Result ½× pixel clock 1× pixel clock 2× pixel clock 90° phase 1× pixel clock 5-4 These two bits select the drive strength for all the high-speed digital outputs (except VSOUT, A0 and O/E field). Higher drive strength results in faster rise/fall times and in general makes it easier to capture data. Lower drive strength results in slower rise/fall times and helps to reduce EMI and digitally generated power supply noise.
AD9880 Table 56. SOGOUT Three-State Table 60. Auto Power-Down Select Select 0 1 Auto Power Down 0 1 Result Auto power down disabled Chip powers down if no sync inputs present 0x27 HDCP A0 Address 0x26 Result Normal I2S output I2S pins in high impedance mode. 3 Power-Down Polarity This bit defines the polarity of the input power-down pin. The power-up default setting is 1. This bit sets the LSB of the address of the HDCP I2C.
AD9880 0x28 1-0 Hsync Delay MSBs Table 66. Detected TMDS Sync Results Along with the eight bits following these ten bits set the delay (in pixels) from the Hsync leading edge to the start of active video. The power-up default setting is 0x104.
AD9880 0x32 Table 71. DVI Hsync Polarity Detect Detect 0 1 0x30 Result DVI Hsync polarity is low active DVI Hsync polarity is high active 4 This read-only bit indicates the polarity of the DVI Vsync. 0x33 Result DVI Vsync polarity is low active DVI Vsync polarity is high active 3-0 0x33 These read-only bits indicate the pixel repetition on DVI. 0 = 1×, 1 = 2×, 2 = 3×, up to a maximum repetition of 10× (0x9).
AD9880 0x38 COLOR SPACE CONVERSION 0x34 0x39 1 0x3A 0x3B This bit enables the color space converter. The powerup default setting is 0. Select 0 1 Result Disable color space converter Enable color space converter 6-5 Color space Converter Mode 0x44 0x45 7-0 4-0 CSC B2 LSBs CSC B3 MSBs 7-0 4-0 CSC B3 LSBs CSC B4 MSBs 7-0 4-0 CSC B4 LSBs CSC C1 MSBs 0x46 0x47 7-0 4-0 CSC C1 LSBs CSC C2 MSBs 7-0 4-0 CSC C2 LSBs CSC C3 MSBs The default value for the 13-bit C3 is 0x0E87.
AD9880 Table 76. PLL_N [2:0] 0 1 2 3 4 5 6 7 0x58 3 Table 78. MCLK Divide Value /1 /2 /3 /4 /5 /6 /7 /8 Packet Detect Bit 0 1 2 3 4 5 6 0x5B N_CTS_Disable 2-0 MCLK fs_N These bits control the multiple of 128 fs used for MCLK out. Table 77. MCLK fs_N [2:0] 0 1 2 3 4 5 6 7 0x59 6 fs Multiple 128 256 384 512 640 768 896 1024 5 4 MDA/MCL PU Disable CLK Term O/R 2 0x62 0x7B 1 FIFO Reset OF This bit resets the audio FIFO if overflow is detected.
AD9880 0x85 Table 80. Y 00 01 10 Video Data RGB YCbCr 4:2:2 YCbCr 4:4:4 0x81 4 Active Format Information Present 3-2 0x86 Bar Information Bar Type No bar information Horizontal bar information valid Vertical bar information valid Horizontal and vertical bar information valid 0x81 1-0 0x87 Scan Information Scan Type No information Overscanned (television) Underscanned (computer) 0x82 7-6 Colorimetry Table 83.
AD9880 0x8D 7-0 Active Pixel End LSB 0x91 Combined with the MSB in Register 0x8E these bits indicate the last active video pixel in the display. All pixels past this comprise a right vertical bar. If the 2-byte value is greater than the number of pixels in the display, there is no vertical bar. 0x8E 7-0 Active Pixel End MSB See Register 0x8D. 0x8F 6-0 NDF See Register 0x87.
AD9880 Table 91.
AD9880 0xA0 0xA1 0xA2 7-0 7-0 7-0 VN7 VN8 Product Description Character 1 (PD1) This is the first character of 16 which contains the model number and a short description of the product. The data characters are 7-bit ASCII code. 0xA3 0xA4 0xA5 0xA6 0xA7 7-0 7-0 7-0 7-0 6-0 PD2 PD3 PD4 PD5 New Data Flags See Register 0x87 for a description. 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 7-0 7-0 7-0 7-0 7-0 7-0 7-0 6-0 PD6 PD7 PD8 PD9 PD10 PD11 PD12 New Data Flags See Register 0x87 for a description.
AD9880 Table 96. ISRC1 Valid 0 1 Description ISRC1 status bits and PBs not valid ISRC1 status bits and PBs valid 0xC8 ISRC Status 2-0 0xD9 0xDA 0xDB 0xDC These bits define where in the ISRC track the samples are: at least two transmissions of 001 occur at the beginning of the track, while in the middle of the track, continuous transmission of 010 occurs followed by at least two transmissions of 100 near the end of the track.
AD9880 2-WIRE SERIAL CONTROL PORT Data Transfer via Serial Interface A 2-wire serial interface control interface is provided in the AD9880. Up to two AD9880 devices can be connected to the 2-wire serial interface, with a unique address for each device. For each byte of data read or written, the MSB is the first bit of the sequence. The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin.
AD9880 SDA tBUFF tDSU tDHO tSTAH tSTASU tSTOSU tDAL 05087-007 SCL tDAH Figure 17.
AD9880 PCB LAYOUT RECOMMENDATIONS The AD9880 is a high-precision, high-speed analog device. To achieve the maximum performance from the part, it is important to have a well laid-out board. The following is a guide for designing a board using the AD9880. Analog Interface Inputs Using the following layout techniques on the graphics inputs is extremely important: • Minimize the trace length running into the graphics inputs.
AD9880 Outputs (Both Data and Clocks) Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which require more current that causes more internal digital noise. Shorter traces reduce the possibility of reflections. keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside of the AD9880 and creates more digital noise on its power supplies.
AD9880 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 98.
AD9880 Table 102.
AD9880 OUTLINE DIMENSIONS 16.00 BSC SQ 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 25 51 50 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 19.
AD9880 NOTES Rev.
AD9880 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05087–0–8/05(0) Rev.
