Datasheet

AD9858
Rev. C | Page 5 of 32
Parameter Temp Test Level Min Typ Max Unit
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency Full IV 10 MHz
Minimum Clock Pulse Width Low (t
PWL
) Full IV 5.5 ns
Minimum Clock Pulse Width High (t
PWH
) Full IV 15 ns
Maximum Clock Rise/Fall Time Full IV 1 ns
Minimum Data Setup Time (t
DS
) Full IV 7 ns
Minimum Data Hold Time (t
DH
) Full IV 0 ns
Maximum Data Valid Time (t
DV
) Full IV 20 ns
Parallel Control Bus
10
WR Minimum Low Time (t
WRLOW
)
Full IV 3 ns
WR Minimum High Time (t
WRHIGH
)
Full IV 6 ns
WR Minimum Period (t
WR
)
Full IV 9 ns
Address to WR Setup (t
ASU
)
Full IV 3 ns
Address to WR Hold (t
AHU
)
Full IV 0 ns
Data to WR Setup (t
DSU
)
Full IV 3.5 ns
Data to WR Hold (t
DHU
)
Full IV 0 ns
Miscellaneous Timing Specifications
REFCLK to SYNCLK Full V 2.5 ns
FUD/PS[1:0] to SYNCLK Setup Time
11
Full IV 4 ns
FUD/PS[1:0] to SYNCLK Hold Time
11
Full IV 0 ns
REFCLK to SYNCLK Delay Full IV 2.5 3 ns
DATA LATENCY (PIPELINE DELAY)
FTW/POW to DAC Output 25°C IV 83 83
SYSCLK
cycles
12
DFTW to DAC Output 25°C IV 99 99
SYSCLK
cycles
12
1
REFCLK input is internally dc biased. AC coupling should be used.
2
Reference clock frequency is selected to ensure that the second harmonic is out of the bandwidth of interest.
3
PD inputs set at 400 MHz with divide-by-4 enabled.
4
The charge pump current is programmable in eight discrete steps; minimum value assumes current sharing.
5
For 0.75 V < V
CP
< CPV
DD
− 0.75 V.
6
These differential inputs are internally dc biased. AC coupling should be used.
7
The charge pump supply voltage can range from 4.75 V to 5.25 V.
8
DAC output is differential open collector.
9
For 1 dB output compression; input power measured at 50 Ω.
10
See Figure 35 and Figure 36 for timing diagrams.
11
See Figure 34 for timing diagram.
12
SYSCLK = REFCLK/x, where x is 1 or 2, as set using CFR[6].