Datasheet

AD9858
Rev. C | Page 4 of 32
Parameter Temp Test Level Min Typ Max Unit
OUTPUT PHASE NOISE CHARACTERISTICS
(AT 100 MHz I
OUT
With 700 MHz REFCLK)
At 100 Hz Offset Full V –125 dBc/Hz
At 1 kHz Offset Full V –140 dBc/Hz
At 10 kHz Offset Full V –148 dBc/Hz
At 100 kHz Offset Full V –150 dBc/Hz
At 1 MHz Offset Full V –150 dBc/Hz
At 10 MHz Offset Full V –150 dBc/Hz
PHASE DETECTOR AND CHARGE PUMP
Phase Detector Frequency Full VI 150 MHz
Phase Detector Frequency (Divide-by-4 Enabled)
3
Full VI 400 MHz
Charge Pump Sink and Source Current
4
Full VI 4 mA
Fast Lock Current (Acquisition Only) Full VI 7 mA
Open-Loop Current (Acquisition Only) Full VI 30 mA
Sink and Source Current Absolute Accuracy
5
Full V 2.5 %
Sink and Source Current Matching
5
Full V 1 %
Input Sensitivity PD
IN
and DIV
IN
(50 Ω)
6
Full IV –15 0 dBm
Input Impedance PD
IN
and DIV
IN
(Single-Ended) Full V 1 kΩ
Phase Noise @ 100 MHz Input Frequency
At 10 kHz Offset Full V 110 dBc/Hz
At 100 kHz Offset Full V 140 dBc/Hz
At 1 MHz Offset Full V 148 dBc/Hz
Charge Pump Output Range
7
Full V CPV
DD
V
MIXER
IF
OUT
8
Full V 400 MHz
f
RF
Full VI 2 GHz
f
LO
Full VI 2 GHz
Conversion Gain Full VI 0.0 3.5 dB
LO Level Full VI –10 +5 dBm
RF Level Full VI –20 dBm
Input IP3 Full VI 5 9 dBm
1 dB Input Compression Power
9
Full VI –3 dBm
Input Impedance (Single-Ended)
LO Full V 1 kΩ
RF Full V 1 kΩ
CMOS LOGIC INPUTS
Logic 1 Voltage Full VI 2.0 V
Logic 0 Voltage Full VI 0.8 V
Logic 1 Current Full VI 12 μA
Logic 0 Current Full VI 12 μA
Input Capacitance Full V 3 pF
CMOS LOGIC OUTPUTS (1 mA LOAD)
Logic 1 Voltage Full VI 2.8 V
Logic 0 Voltage Full VI 0.4 V
POWER DISSIPATION
P
DISS
(Worst-Case Conditions—Everything on
P
FD
Input Frequency 150 MHz)
Full VI 2 2.5 W
P
DISS
(DAC and DDS Core Only Worst-Case) Full VI 1.7 2 W
P
DISS
(Power-Down Mode) Full VI 65 100 mW
P
DISS
Mixer Only Full VI 60 75 mW
P
DISS
PFD and CP (at 100 MHz) Only Full VI 350 435 mW