CMOS 300 MSPS Quadrature Complete DDS AD9854 FEATURES Automatic bidirectional frequency sweeping Sin(x)/x correction Simplified control interfaces 10 MHz serial 2- or 3-wire SPI compatible 100 MHz parallel 8-bit programming 3.
AD9854 TABLE OF CONTENTS Features .............................................................................................. 1 Programming the AD9854............................................................ 32 Applications....................................................................................... 1 MASTER RESET ........................................................................ 32 Functional Block Diagram ..............................................................
AD9854 REVISION HISTORY 7/07—Rev. D to Rev. E Changed AD9854ASQ to AD9854ASVZ ....................... Universal Changed AD9854AST to AD9854ASTZ......................... Universal Changes to General Description .....................................................4 Changes to Table 1 Endnotes...........................................................7 Changes to Absolute Maximum Ratings Section..........................8 Changes to Power Dissipation Section.........................................
AD9854 GENERAL DESCRIPTION The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high speed, high performance quadrature DACs to form a digitally programmable I and Q synthesizer function. When referenced to an accurate clock source, the AD9854 generates highly stable, frequency-phase, amplitude-programmable sine and cosine outputs that can be used as an agile LO in communications, radar, and many other applications.
AD9854 SPECIFICATIONS VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ, external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted. Table 1.
AD9854 Parameter Residual Phase Noise (AOUT = 5 MHz, External Clock = 30 MHz REFCLK Multiplier Engaged at 10×) 1 kHz Offset 10 kHz Offset 100 kHz Offset (AOUT = 5 MHz, External Clock = 300 MHz, REFCLK Multiplier Bypassed) 1 kHz Offset 10 kHz Offset 100 kHz Offset PIPELINE DELAYS 4, 5, 6 DDS Core (Phase Accumulator and Phase-to-Amp Converter) Frequency Accumulator Inverse Sinc Filter Digital Multiplier DAC I/O Update Clock (Internal Mode) I/O Update Clock (External Mode) MASTER RESET DURATION COMPARATOR INPU
AD9854 Parameter PARALLEL I/O TIMING CHARACTERISTICS tASU (Address Setup Time to WR Signal Active) tADHW (Address Hold Time to WR Signal Inactive) tDSU (Data Setup Time to WR Signal Inactive) tDHD (Data Hold Time to WR Signal Inactive) tWRLOW (WR Signal Minimum Low Time) tWRHIGH (WR Signal Minimum High Time) tWR (Minimum WR Time) tADV (Address to Data Valid Time) tADHR (Address Hold Time to RD Signal Inactive) tRDLOV (RD Low to Output Valid) tRDHOZ (RD High to Data Three-State) SERIAL I/O TIMING CHARACTERIS
AD9854 ABSOLUTE MAXIMUM RATINGS To determine the junction temperature on the application PCB use the following equation: Table 2. Parameter Maximum Junction Temperature VS Digital Inputs Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Maximum Clock Frequency (ASVZ) Maximum Clock Frequency (ASTZ) Rating 150°C 4V −0.
AD9854 PLL FILTER AGND NC DIFF CLK ENABLE AVDD AGND AGND REFCLK REFCLK S/P SELECT MASTER RESET DGND DVDD DVDD DGND DGND DGND DGND DVDD DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 AVDD D7 1 D6 2 D5 3 58 NC D4 4 57 NC D3 5 D2 6 56 DAC R SET 55 DACBP D1 7 54 AVDD D0 8 53 AGND DVDD 9 PIN 1 INDICATOR 59 AGND 52 IOUT2 AD9854 DVDD 10 51 IOUT2 TOP VIEW (Not to Scale) DGND 11 DGND 12 50 AVDD 49 I
AD9854 Pin No. 20 Mnemonic I/O UD CLK 21 WR/SCLK 22 RD/CS 29 FSK/BPSK/HOLD 30 OSK 31, 32, 37, 38, 44, 50, 54, 60, 65 33, 34, 39, 40, 41, 45, 46, 47, 53, 59, 62, 66, 67 36 AVDD 42 43 48 49 51 52 VINP VINN IOUT1 IOUT1 IOUT2 IOUT2 55 DACBP 56 DAC RSET 61 PLL FILTER 64 DIFF CLK ENABLE 68 REFCLK 69 REFCLK 70 71 S/P SELECT MASTER RESET AGND VOUT Description Bidirectional I/O Update Clock. Direction is selected in control register.
AD9854 DVDD AVDD AVDD IOUT IOUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC OUTPUTS COMPARATOR OUT VINP/ VINN B. COMPARATOR OUTPUT C. COMPARATOR INPUT Figure 3. Equivalent Input and Output Circuits Rev. E | Page 11 of 52 DIGITAL IN AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. D.
AD9854 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from 0 MHz to 150 MHz (Nyquist).
AD9854 Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of sampling the fundamental at a higher rate.
AD9854 Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 200 MHz reference clock with the REFCLK multiplier bypassed vs. a 20 MHz reference clock and the REFCLK multiplier enabled at 10×. 0 –90 –10 –100 –20 PHASE NOISE (dBc/Hz) –30 –40 –50 –60 –70 AOUT = 80MHz –110 –120 –130 –140 –80 –150 AOUT = 5MHz CENTER 39.1MHz 5kHz/ SPAN 50kHz –160 10 100 1k 10k FREQUENCY (Hz) 100k 00636-019 –100 00636-016 –90 1M Figure 19.
AD9854 1200 MINIMUM COMPARATOR INPUT DRIVE VCM = 0.5V AMPLITUDE (mV p-p) 1000 RISE TIME 1.04ns JITTER [10.6ps RMS] 800 600 400 200 232mV/DIV +33ps 50Ω INPUT 0 Figure 22. Typical Comparator Output Jitter, 40 MHz AOUT, 300 MHz RFCLK with REFCLK Multiplier Bypassed M 500ps CH1 980mV 00636-023 C1 FALL 1.286ns 500mVΩ 100 200 300 FREQUENCY (MHz) 400 Figure 24. Comparator Toggle Voltage Requirement REF1 RISE 1.174ns CH1 0 Figure 23. Comparator Rise/Fall Times Rev.
AD9854 TYPICAL APPLICATIONS I BASEBAND LPF REFCLK COS LPF AD9854 LPF SIN CHANNEL SELECT FILTERS 00636-025 RF/IF INPUT Q BASEBAND LPF Figure 25. Quadrature Downconversion I BASEBAND AD9854 RF OUTPUT LPF SIN 00636-026 REFCLK COS LPF Q BASEBAND Figure 26.
AD9854 REFERENCE CLOCK PHASE COMPARATOR LOOP FILTER AD9854 REF CLK IN RF FREQUENCY OUT VCO DAC OUT DDS PROGRAMMABLE DIVIDE-BY-N FUNCTION (WHERE N = 248/TUNING WORD) TUNING WORD 00636-029 FILTER Figure 29. Programmable Fractional Divide-by-N Synthesizer REF CLOCK FILTER DDS PHASE COMPARATOR TUNING WORD RF FREQUENCY OUT VCO LOOP FILTER 00636-030 AD9854 DIVIDE-BY-N Figure 30.
AD9854 COMPARATORS AOUT = 100MHz REFERENCE CLOCK LPF SIN AD9854 CLOCK OUT = 200MHz 00636-033 LPF COS Figure 33. Clock Frequency Doubler REFERENCE CLOCK 2kΩ 300MHz MAX DIRECT MODE OR 15MHz TO 75MHz MAX IN THE 4× TO 20× CLOCK MULTIPLIER MODE LOW-PASS FILTER I DAC 1 Q DAC OR CONTROL DAC 2 LOW-PASS FILTER + RSET NOTES 1. IOUT = APPROX 20mA MAX WHEN RSET = 2kΩ. 2. SWITCH POSITION 1 PROVIDES COMPLEMENTARY SINUSOIDAL SIGNALS TO THE COMPARATOR TO PRODUCE A FIXED 50% DUTY CYCLE FROM THE COMPARATOR. 3.
AD9854 THEORY OF OPERATION The AD9854 quadrature output digital synthesizer is a highly flexible device that addresses a wide range of applications. The device consists of an NCO with a 48-bit phase accumulator, a programmable reference clock multiplier, inverse sinc filters, digital multipliers, two 12-bit/300 MHz DACs, a high speed analog comparator, and interface logic. This highly integrated device can be configured to serve as a synthesized LO, an agile clock generator, or an FSK/BPSK modulator.
FREQUENCY AD9854 F1 0 MODE TW1 000 (DEFAULT) 000 (SINGLE TONE) 0 F1 00636-035 MASTER RESET I/O UD CLK Figure 35. Default State to User-Defined Output Transition a 10 MHz serial rate. Incorporating this attribute permits FM, AM, PM, FSK, PSK, and ASK operation in single-tone mode.
AD9854 FREQUENCY F2 F1 0 000 (DEFAULT) 001 (FSK NO RAMP) TW1 0 F1 TW2 0 F2 MODE 00636-036 I/O UD CLK FSK DATA (PIN 29) Figure 36. Unramped (Traditional) FSK Mode FREQUENCY F2 F1 0 000 (DEFAULT) 010 (RAMPED FSK) TW1 0 F1 TW2 0 F2 MODE REQUIRES A POSITIVE TWOS COMPLEMENT VALUE DFW RAMP RATE 00636-037 I/O UD CLK FSK DATA (PIN 29) Figure 37.
AD9854 Note that in ramped FSK mode, the delta frequency word (DFW) is required to be programmed as a positive twos complement value. Another requirement is that the lowest frequency (F1) be programmed in the Frequency Tuning Word 1 register. The purpose of ramped FSK is to provide better bandwidth containment than traditional FSK by replacing the instantaneous frequency changes with more gradual, user-defined frequency changes.
AD9854 FREQUENCY F2 F1 0 MODE 010 (RAMPED FSK) TW1 F1 TW2 F2 FSK DATA 00636-040 TRIANGLE BIT I/O UD CLK Figure 40. Effect of Triangle Bit in Ramped FSK Mode FREQUENCY F2 F1 0 000 (DEFAULT) 010 (RAMPED FSK) TW1 0 F1 TW2 0 F2 MODE 00636-041 I/O UD CLK FSK DATA Figure 41. Effect of Premature Ramped FSK Data Figure 41 shows that premature toggling causes the ramp to immediately reverse itself and proceed at the same rate and resolution until the original frequency is reached.
AD9854 the 32-bit internal update clock (see the Internal and External Update Clock section). Nonlinear ramped FSK has the appearance of the chirp function shown in Figure 43. The difference between a ramped FSK function and a chirp function is that FSK is limited to operation between F1 and F2, whereas chirp operation has no F2 limit frequency. Two additional control bits (CLR ACC1 and CLR ACC2) are available in the ramped FSK mode that allow more options.
AD9854 The AD9854 permits precise, internally generated linear, or externally programmed nonlinear, pulsed or continuous FM over the complete frequency range, duration, frequency resolution, and sweep direction(s). All of these are user programmable. Figure 44 shows a block diagram of the FM chirp components. Two control bits (CLR ACC1 and CLR ACC2) are available in the FM chirp mode that allow the return to the beginning frequency, FTW1, or to 0 Hz.
FREQUENCY AD9854 F1 0 MODE 000 (DEFAULT) 011 (CHIRP) FTW1 0 F1 DELTA FREQUENCY WORD DFW RAMP RATE RAMP RATE 00636-045 I/O UD CLK CLR ACC1 FREQUENCY Figure 45. Effect of CLR ACC1 in FM Chirp Mode F1 0 MODE TW1 000 (DEFAULT) 011 (CHIRP) 0 DPW RAMP RATE 00636-046 CLR ACC2 I/O UD CLK Figure 46. Effect of CLR ACC2 in Chirp Mode Rev.
FREQUENCY AD9854 F1 0 MODE 000 (DEFAULT) 011 (CHIRP) 0 F1 TW1 DELTA FREQUENCY WORD DFW RAMP RATE RAMP RATE 00636-047 HOLD I/O UD CLK Figure 47. Example of Hold Function PHASE 360 0 MODE 000 (DEFAULT) 100 (BPSK) FTW1 0 F1 PHASE ADJUST 1 270° PHASE ADJUST 2 90° 00636-048 BPSK DATA I/O UD CLK Figure 48. BPSK Mode The 32-bit automatic I/O update counter can be used to construct complex chirp or ramped FSK sequences.
AD9854 • Continue chirp by immediately returning to the beginning frequency (F1) in a sawtooth fashion, and then repeating the previous chirp process using the CLR ACC1 control bit. An automatic, repeating chirp can be set up by using the 32-bit update clock to issue the CLR ACC1 command at precise time intervals. Adjusting the timing intervals or changing the delta frequency word changes the chirp range.
AD9854 USING THE AD9854 INTERNAL AND EXTERNAL UPDATE CLOCK ON/OFF OUTPUT SHAPED KEYING (OSK) This update clock function is comprised of a bidirectional I/O pin (Pin 20) and a programmable 32-bit down-counter. To program changes that are to be transferred from the I/O buffer registers to the active core of the DDS, a clock signal (low-tohigh edge) must be externally supplied to Pin 20 or internally generated by the 32-bit update clock. The on/off OSK feature allows the user to control the amplitude vs.
AD9854 (BYPASS MULTIPLIER) OSK EN = 0 OSK EN = 0 12-BIT DIGITAL MULTIPLIER 12 12 USER-PROGRAMMABLE 12-BIT Q CHANNEL MULTIPLIER OUTPUT SHAPED KEYING Q MULTIPLIER REGISTER SINE DAC OSK EN = 1 OSK EN = 1 12 OSK INT = 0 12 OSK INT = 0 12 12-BIT UP/DOWN COUNTER 1 8-BIT RAMP RATE COUNTER ON/OFF OUTPUT SHAPED KEYING PIN SYSTEM CLOCK 00636-050 DDS DIGITAL OUTPUT DIGITAL SIGNAL IN Figure 50.
AD9854 INVERSE SINC FUNCTION The inverse sinc function precompensates input data to both DACs for the sin(x)/x roll-off characteristic inherent in the DAC’s output spectrum. This allows wide bandwidth signals (such as QPSK) to be output from the DACs without appreciable amplitude variations as a function of frequency. The inverse sinc function can be bypassed to reduce power consumption significantly, especially at higher clock speeds.
AD9854 PROGRAMMING THE AD9854 The AD9854 register layout table (Table 8) contains information for programming the chip for the desired functionality. Although many applications require very little programming to configure the AD9854, some use all 12 accessible register banks. The AD9854 supports an 8-bit parallel I/O operation or an SPI®compatible serial I/O operation. All accessible registers can be written and read back in either I/O operating mode. S/P SELECT (Pin 70) is used to configure the I/O mode.
AD9854 Table 8.
AD9854 PARALLEL I/O OPERATION With the S/P SELECT pin tied high, the parallel I/O mode is active. The I/O port is compatible with industry-standard DSPs and microcontrollers. Six address bits, eight bidirectional data bits, and separate write/read control inputs comprise the I/O port pins. Parallel I/O operation allows write access to each byte of any register in a single I/O operation of up to one per 10.5 ns. Readback capability for each register is included to ease designing with the AD9854.
AD9854 A<5:0> A1 A2 A3 D<7:0> D1 D2 D3 RD t RDHOZ t RDLOV t ADV SPECIFICATION VALUE DESCRIPTION t ADV t AHD t RDLOV t RDHOZ 15ns 5ns 15ns 10ns ADDRESS TO DATA VALID TIME (MAXIMUM) ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM) RD LOW TO OUTPUT VALID (MAXIMUM) RD HIGH TO DATA THREE-STATE (MAXIMUM) 00636-052 t AHD Figure 52.
AD9854 GENERAL OPERATION OF THE SERIAL INTERFACE transferred.) The AD9854 internal serial I/O controller expects every byte of the register being accessed to be transferred. Therefore, the user should write between I/O update clocks. There are two phases of a serial communication cycle with the AD9854. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9854 coincident with the first eight SCLK rising edges.
AD9854 INSTRUCTION BYTE NOTES ON SERIAL PORT OPERATION The instruction byte contains the following information: The AD9854 serial port configuration bits reside in Bit 1 and Bit 0 of Register Address 20 hex. It is important to note that the configuration changes immediately upon a valid I/O update. For multibyte transfers, writing to this register can occur during the middle of a communication cycle. The user must compensate for this new configuration for the remainder of the current communication cycle.
AD9854 MSB/LSB TRANSFERS The AD9854 serial port can support MSB- and LSB-first data formats. This functionality is controlled by Bit 1 of Serial Register Bank 20 hex. When this bit is set active high, the AD9854 serial port is in LSB-first format. This bit defaults low, to the MSB-first format. The instruction byte must be written in the format indicated by Bit 1 of Serial Register Bank 20 hex.
AD9854 DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SDIO I7 I6 I5 I4 I3 I2 I1 I0 D6 D7 D5 D4 D3 D2 D1 00636-058 SCLK D0 Figure 58. Serial Port Write Timing Clock Stall Low DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK I7 I6 I4 I5 I3 I2 I1 I0 DON'T CARE DO7 SDO DO6 DO5 DO4 DO3 DO2 DO1 00636-059 SDIO DO0 Figure 59.
AD9854 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9854 is a multifunctional, high speed device that targets a wide variety of synthesizer and agile clock applications. The numerous innovative features contained in the device each consume incremental power. If enabled in combination, the safe thermal operating conditions of the device may be exceeded. Careful analysis and consideration of power dissipation and thermal management is a critical element in the successful application of the AD9854.
AD9854 multipliers, the inverse sinc filter, the Q DAC, and the on-board comparator are disabled. 1400 1200 SUPPLY CURRENT (mA) ALL CIRCUITS ENABLED 1000 The first step in applying the AD9854 is to select the internal clock frequency. Clock frequency selections greater than 200 MHz require the use of the thermally enhanced package (AD9854ASVZ); other clock frequencies may allow the use of the standard plastic surface-mount package, but more information is needed to make that determination.
AD9854 EVALUATION BOARD An evaluation board package is available for the AD9854 DDS device. This package consists of a PCB, software, and documentation to facilitate bench analysis of the device’s performance. To ensure optimum dynamic performance from the device, users should familiarize themselves with the operation and performance capabilities of the AD9854 with the evaluation board and use the evaluation board as a PCB reference design.
AD9854 attached to each header to allow the DAC signals to be routed to the filters. If the user wishes to test the filters, the shorting jumpers at W7 and W10 should be removed and 50 Ω test signals should be applied at the J4 and J5 inputs to the 50 Ω elliptic filters. Users should refer to the schematic provided and to the following sections to properly position the remaining shorting jumpers. The resulting I and Q signals appear as nearly pure sine waves and 90° out of phase with each other.
AD9854 output current from 10 mA to 20 mA and doubles the peak-topeak output voltage developed across the loads, thus resulting in more robust signals at the comparator inputs. Single-Ended Configuration To connect the high speed comparator in a single-ended configuration so that the duty cycle or pulse width can be controlled, a dc threshold voltage must be present at one of the comparator inputs. The user can supply this voltage using the control DAC.
AD9854 Table 12.
AD9854 Item 27 Qty 1 Reference Designator U3 28 4 29 Device Primary Secondary Package 8 SOIC 8 SOIC Value N/A N/A Min Tol N/A N/A U4, U5, U6, U7 74HC14 14 SOIC N/A N/A 3 U8, U9, U10 74HC574 20 SOIC N/A N/A 30 1 J11 C36CRPX 36CRP N/A N/A 31 6 3-pin header SIP-3P N/A 32 10 2-pin header SIP-2P 33 6 Jumpers 34 10 35 2 W1, W2, W3, W4, W8, W17 W6, W7, W9, W10, W11, W12, W13, W14, W15, W16 W1, W2, W3, W4, W8, W17 W6, W7, W9, W10, W11, W12, W13, W14, W15, W16 N/A 36 37 3
GND AVDD CLK8 CLK RESET DVDD 1 AVDD 50 IOUT1 49 IOUT1 48 DGND1 DGND2 NC 11 12 13 ADDR2 ADDR1 17 18 19 20 A1/SDO A0/SDIO I/O UD CLK GND J10 ADDR3 16 A3 A2/IO RESET UPDCLK ADDR0 ADDR4 15 A4 ADDR5 14 A5 NC2 GND DVDD DVDD4 DVDD DVDD3 DVDD RD RD/CS WR/SCLK FDATA 4 3 2 1 GND GND GND VCC DVDD C20 0.1µF C6 10µF C19 0.1µF C18 0.1µF C17 0.1µF J15 J16 J17 J18 J19 J20 J22 J24 1 W7 C16 0.1µF J25 C12 0.1µF 1 GND L6 82nH C30 39pF L2 68nH GND Y1 3.
Rev. E | Page 48 of 52 Figure 65.
00636-070 AD9854 00636-071 Figure 66. Assembly Drawing Figure 67. Top Routing Layer, Layer 1 Rev.
00636-072 AD9854 00636-073 Figure 68. Power Plane Layer, Layer 3 Figure 69. Ground Plane Layer, Layer 2 Rev.
00636-074 AD9854 Figure 70. Bottom Routing Layer, Layer 4 Rev.
AD9854 OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 0.75 0.60 0.45 14.20 14.00 SQ 13.80 1.20 MAX 80 61 1 61 60 80 1 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 0° MIN 1.05 1.00 0.95 SEATING PLANE 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 20 41 21 40 9.50 SQ BOTTOM VIEW (PINS UP) 41 20 21 40 VIEW A 0.65 BSC LEAD PITCH 0.27 0.22 0.17 VIEW A 091506-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AEC-HD Figure 71.
