Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TYPICAL APPLICATIONS
- MODES OF OPERATION
- USING THE AD9852
- PROGRAMMING THE AD9852
- GENERAL OPERATION OF THE SERIAL INTERFACE
- POWER DISSIPATION AND THERMAL CONSIDERATIONS
- EVALUATION OF OPERATING CONDITIONS
- EVALUATION BOARD
- EVALUATION BOARD INSTRUCTIONS
- GENERAL OPERATING INSTRUCTIONS
- Hardware Preparation
- Clock Input, J25
- Three-State Control
- Programming
- Low-Pass Filter Testing
- Observing the Unfiltered IOUT1 and the Unfiltered IOUT2 DAC Signals
- Observing the Filtered IOUT1 and the Filtered IOUT2
- Observing the Filtered IOUT1 and the Filtered IOUT1
- Connecting the High Speed Comparator
- Single-Ended Configuration
- USING THE PROVIDED SOFTWARE
- SUPPORT
- OUTLINE DIMENSIONS

AD9852
Rev. E | Page 6 of 52
Test AD9852ASVZ AD9852ASTZ
Parameter Temp Level Min Typ Max Min Typ Max Unit
Residual Phase Noise
(A
OUT
= 5 MHz, External Clock = 30 MHz,
REFCLK Multiplier Engaged at 10×)
1 kHz Offset 25°C V 140 140 dBc/Hz
10 kHz Offset 25°C V 138 138 dBc/Hz
100 kHz Offset 25°C V 142 142 dBc/Hz
(A
OUT
= 5 MHz, External Clock = 300 MHz,
REFCLK Multiplier Bypassed)
1 kHz Offset 25°C V 142 142 dBc/Hz
0 kHz Offset 25°C V 148 148 dBc/Hz
100 kHz Offset 25°C V 152 152 dBc/Hz
PIPELINE DELAYS
3,
4,
5
DDS Core (Phase Accumulator and
Phase-to-Amp Converter)
25°C IV 33 33 SYSCLK cycles
Frequency Accumulator 25°C IV 26 26 SYSCLK cycles
Inverse Sinc Filter 25°C IV 16 16 SYSCLK cycles
Digital Multiplier 25°C IV 9 9 SYSCLK cycles
DAC 25°C IV 1 1 SYSCLK cycles
I/O Update Clock (Internal Mode) 25°C IV 2 2 SYSCLK cycles
I/O Update Clock (External Mode) 25°C IV 3 3 SYSCLK cycles
MASTER RESET DURATION 25°C IV 10 10 SYSCLK cycles
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance 25°C V 3 3 pF
Input Resistance 25°C IV 500 500 kΩ
Input Current 25°C I ± 1 ± 5 ± 1 ± 5 μA
Hysteresis 25°C IV 10 20 10 20 mV p-p
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High-Z Load Full VI 3.1 3.1 V
Logic 0 Voltage, High-Z Load Full VI 0.16 0.16 V
Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm
Propagation Delay 25°C IV 3 3 ns
Output Duty Cycle Error
6
25°C I −10 ± 1 +10 −10 ± 1 +10 %
Rise/Fall Time, 5 pF Load 25°C V 2 2 ns
Toggle Rate, High-Z Load 25°C IV 300 350 300 350 MHz
Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz
Output Cycle-to-Cycle Jitter
7
25°C IV 4.0 4.0 ps rms
COMPARATOR NARROW-BAND SFDR
8
10 MHz (±1 MHz) 25°C V 84 84 dBc
10 MHz (±250 MHz) 25°C V 84 84 dBc
10 MHz (±50 kHz) 25°C V 92 92 dBc
41 MHz (±1 MHz) 25°C V 76 76 dBc
41 MHz (±250 kHz) 25°C V 82 82 dBc
41 MHz (±50 kHz) 25°C V 89 89 dBc
119 MHz (±1 MHz) 25°C V 73 dBc
119 MHz (±250 kHz) 25°C V 73 dBc
119 MHz (±50 kHz) 25°C V 83 dBc
CLOCK GENERATOR OUTPUT JITTER
8
5 MHz A
OUT
25°C V 23 23 ps rms
40 MHz A
OUT
25°C V 12 12 ps rms
100 MHz A
OUT
25°C V 7 7 ps rms