Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TYPICAL APPLICATIONS
- MODES OF OPERATION
- USING THE AD9852
- PROGRAMMING THE AD9852
- GENERAL OPERATION OF THE SERIAL INTERFACE
- POWER DISSIPATION AND THERMAL CONSIDERATIONS
- EVALUATION OF OPERATING CONDITIONS
- EVALUATION BOARD
- EVALUATION BOARD INSTRUCTIONS
- GENERAL OPERATING INSTRUCTIONS
- Hardware Preparation
- Clock Input, J25
- Three-State Control
- Programming
- Low-Pass Filter Testing
- Observing the Unfiltered IOUT1 and the Unfiltered IOUT2 DAC Signals
- Observing the Filtered IOUT1 and the Filtered IOUT2
- Observing the Filtered IOUT1 and the Filtered IOUT1
- Connecting the High Speed Comparator
- Single-Ended Configuration
- USING THE PROVIDED SOFTWARE
- SUPPORT
- OUTLINE DIMENSIONS
AD9852
Rev. E | Page 5 of 52
SPECIFICATIONS
V
S
= 3.3 V ± 5%, R
SET
= 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASVZ,
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852ASTZ, unless otherwise noted.
Table 1.
Test AD9852ASVZ AD9852ASTZ
Parameter Temp Level Min Typ Max Min Typ Max Unit
REFERENCE CLOCK INPUT CHARACTERISTICS
1
Internal System Clock Frequency Range
REFCLK Multiplier Enabled Full VI 20 300 20 200 MHz
REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz
External Reference Clock Frequency Range
REFCLK Multiplier Enabled Full VI 5 75 5 50 MHz
REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz
Duty Cycle 25°C IV 45 50 55 45 50 55 %
Input Capacitance 25°C IV 3 3 pF
Input Impedance 25°C IV 100 100 kΩ
Differential Common-Mode Voltage Range
Minimum Signal Amplitude
2
25°C IV 400 400 mV p-p
Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V
V
IH
(Single-Ended Mode) 25°C IV 2.3 2.3 V
V
IL
(Single-Ended Mode) 25°C IV 1 1 V
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed Full I 300 200 MSPS
Resolution 25°C IV 12 12 Bits
Cosine and Control DAC Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA
Gain Error 25°C I −6
+2.2
5
−6
+2.2
5
% FS
Output Offset 25°C I 2 2 μA
Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB
Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB
Output Impedance 25°C IV 100 100 kΩ
Voltage Compliance Range 25°C I −0.5 +1.0 −0.5 +1.0 V
DAC DYNAMIC OUTPUT CHARACTERISTICS
DAC Wideband SFDR
1 MHz to 20 MHz A
OUT
25°C V 58 58 dBc
20 MHz to 40 MHz A
OUT
25°C V 56 56 dBc
40 MHz to 60 MHz A
OUT
25°C V 52 52 dBc
60 MHz to 80 MHz A
OUT
25°C V 48 48 dBc
80 MHz to 100 MHz A
OUT
25°C V 48 48 dBc
100 MHz to 120 MHz A
OUT
25°C V 48 dBc
DAC Narrow-Band SFDR
10 MHz A
OUT
(±1 MHz) 25°C V 83 83 dBc
10 MHz A
OUT
(±250 kHz) 25°C V 83 83 dBc
10 MHz A
OUT
(±50 kHz) 25°C V 91 91 dBc
41 MHz A
OUT
(±1 MHz) 25°C V 82 82 dBc
41 MHz A
OUT
(±250 kHz) 25°C V 84 84 dBc
41 MHz A
OUT
(±50 kHz) 25°C V 89 89 dBc
119 MHz A
OUT
(±1 MHz) 25°C V 71 dBc
119 MHz A
OUT
(±250 kHz) 25°C V 77 dBc
119 MHz A
OUT
(±50 kHz) 25°C V 83 dBc