Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TYPICAL APPLICATIONS
- MODES OF OPERATION
- USING THE AD9852
- PROGRAMMING THE AD9852
- GENERAL OPERATION OF THE SERIAL INTERFACE
- POWER DISSIPATION AND THERMAL CONSIDERATIONS
- EVALUATION OF OPERATING CONDITIONS
- EVALUATION BOARD
- EVALUATION BOARD INSTRUCTIONS
- GENERAL OPERATING INSTRUCTIONS
- Hardware Preparation
- Clock Input, J25
- Three-State Control
- Programming
- Low-Pass Filter Testing
- Observing the Unfiltered IOUT1 and the Unfiltered IOUT2 DAC Signals
- Observing the Filtered IOUT1 and the Filtered IOUT2
- Observing the Filtered IOUT1 and the Filtered IOUT1
- Connecting the High Speed Comparator
- Single-Ended Configuration
- USING THE PROVIDED SOFTWARE
- SUPPORT
- OUTLINE DIMENSIONS

AD9852
Rev. E | Page 46 of 52
RD/CS
D7
D6
D5
D4
D3
D2
D1
D0
DVDD1
DVDD2
DGND1
DGND2
NC
ADDR5
ADDR4
ADDR3
A2/IO RESET
A1/SDO
A0/SDIO
UPDCLK
U1
AD9852
TOP VIEW
(Not to Scale)
PLLVDD
PLLGND
NC4
NC3
RSET
DACBYPASS
AVDD2
AGND2
IOUT2
IOUT2
AVDD
IOUT1
IOUT1
AGND
GND2
COMPVDD
VINN
VINP
GND
COMPGND
PLLFLT
GND3
NC5
DIFFCLKEN
CLKVDD
CLKGND
GND4
REFCLK
SPSELECT
MRESET
OPTGND
DVDD6
DVDD7
DGND6
DGND7
DGND8
DGND9
DVDD8
DVDD9
COUTGND2
COUTGND
COUTVDD2
COUTVDD
VOUT
NC2
DACDGND2
DACDGND
DACDVDD2
DACDVDD
OSK
FSK/BPSK/HOLD
DGND5
DGND4
DVDD5
DVDD4
DVDD3
RD
DGND3
WR
J6
J8
J16
J17
J18
J19
J20
J21
J22
J24
J23
J14
J13
J12
J11
GND
J15
W6
R2
3.92kΩ
R20
3.92kΩ
AVDD
C45
0.01μF
R1
49.9Ω
J4
W7
W1
1
GND
GND
AVDD
R3
24.9Ω
W10 W16
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
DVDD
GND
GND
A5
A4
A3
A2/IO RESET
A1/SDO
A0/SDIO
I/O UD CLK
AVDD
AVDD
AVDD
DVDD
DVDD
DVDD
OSK
AVDD
AVDD
AVDD
AVDD
AVDD
DVDD
AVDD
GND
DVDD
W3
R4
1.3kΩ
C1
0.01μF
CLK8
CLK
PMODE
RESET
GND
GND
DVDD
GND
R13
49.9Ω
C2
0.01μF
OUT GND
NC3.3V
MC100LVEL16DGOS
L5
68nH
VEE
VBB
VCC
U3
Y1
D
D
Q
Q
DVDD
14
78
1
2
3
7
6
C25
10μF
C21
10μF
C24
0.1μF
C23
0.1μF
C22
0.1μF
C27
0.1μF
C8
0.1μF
C44
0.1μF
GND
DVDD
J10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
UDCLK
WR
RD
PMODE
OSK
RESET
D7
D6
D5
D4
D3
D2
D0
D1
120MHz LOW-PASS FILTER
120MHz LOW-PASS FILTER
W4
R5
49.9Ω
W17
R8
2kΩ
1
DVDD
R11
49.9Ω
R12
49.9Ω
R19
0Ω
R14
0Ω
CLKB
CLK
J3
GND
C37
27pF
C38
47pF
C39
39pF
C40
22pF
W8
1
L1
68nH
L6
82nH
C41
2.2pF
C42
12pF
C43
8.2pF
C31
22pF
C30
39pF
C5
47pF
C4
27pF
L4
82nH
L2
68nH
C32
2.2pF
C33
12pF
C34
8.2pF
GND
J6
W2
1
GND
1
R7
24.9Ω
R6
49.9Ω
FDATA
54
8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND GND
GNDGNDGNDGND
GND
GND
GND
NC = NO CONNECT
L3
68nH
R9
100Ω
GND
R10
100Ω
GND
1
GND
GND
GND
GND
GND
GND
TB1
DVDD
AVDD
VCC
1
2
3
4
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62
61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
40
J26
GND
J1
GND
J5
GND
GND
J7
GND
J25
C6
10μF
C7
0.1μF
C29
0.1μF
C9
0.1μF
C10
0.1μF
C11
0.1μF
C13
0.1μF
GND
AVDD
C20
0.1μF
C19
0.1μF
C18
0.1μF
C14
0.1μF
C26
0.1μF
C28
0.1μF
GND
VCC
C12
0.1μF
C17
0.1μF
C16
0.1μF
J2
GND
WR/SCLK
REFCLK
00634-065
Figure 61. Evaluation Board Schematic