Datasheet

AD9852
Rev. E | Page 37 of 52
SDIO
D
7
I
7
SCLK
CS
INSTRUCTION CYCLE DATA TRANSFER CYCLE
I
6
I
5
I
4
I
3
I
0
I
2
I
1
D
6
D
5
D
4
D
3
D
2
D
1
D
0
00634-055
Figure 55. Serial Port Write Timing Clock Stall Low
SDIO
D
O7
D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
SCLK
CS
INSTRUCTION CYCLE
DON’T CARE
SDO
DATA TRANSFER CYCLE
I
7
I
6
I
5
I
4
I
3
I
0
I
2
I
1
00634-056
Figure 56. 3-Wire Serial Port Read Timing Clock Stall Low
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SDIO
SCLK
INSTRUCTION CYCLE DATA TRANSFER CYCLE
I
7
I
6
I
5
I
4
I
3
I
0
I
2
I
1
CS
00634-057
Figure 57. Serial Port Write Timing Clock Stall High
I
7
I
6
I
5
I
4
I
3
I
0
I
2
I
1
SDIO
SCL
K
INSTRUCTION CYCLE DATA TRANSFER CYCLE
D
O7
D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
CS
00634-058
Figure 58. 2-Wire Serial Port Read Timing Clock Stall High