Datasheet

AD9852
Rev. E | Page 33 of 52
A<5:0>
D<7:0>
RD
A1
D1
A2
D2
A3
D3
t
RDHOZ
t
RDLOV
t
AHD
t
ADV
SPECIFICATION
t
ADV
t
AHD
t
RDLOV
t
RDHOZ
VALUE
15ns
5ns
15ns
10ns
DESCRIPTION
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
00634-049
Figure 49. Parallel Port Read Timing Diagram
D<7:0> D1 D2 D3
SPECIFICATION
t
ASU
t
DSU
t
ADH
t
DHD
t
WRLOW
t
WRHIGH
t
WR
VALUE
8.0ns
3.0ns
0ns
0ns
2.5ns
7ns
10.5ns
DESCRIPTION
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL ACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
MINIMUM WRITE TIME
t
WR
A<5:0> A1 A2 A3
t
ASU
t
AHD
t
WRHIGH
t
WRLOW
t
DHD
t
DSU
WR
00634-050
Figure 50. Parallel Port Write Timing Diagram
Table 10. Serial I/O Pin Requirements
Pin Number Mnemonic Serial I/O Description
1 to 8 D [7:0] The parallel data pins are not active; tie these pins to VDD or GND.
14 to 16 A [5:3] The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND.
17 A2/IO RESET IO RESET.
18 A1/SDO SDO.
19 A0/SDIO SDIO.
20 I/O UD CLK Update Clock. Same functionality for serial mode as parallel mode.
21
WR/SCLK
SCLK.
22
RD/CS CS—Chip Select.