Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- REVISION HISTORY
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TYPICAL APPLICATIONS
- MODES OF OPERATION
- USING THE AD9852
- PROGRAMMING THE AD9852
- GENERAL OPERATION OF THE SERIAL INTERFACE
- POWER DISSIPATION AND THERMAL CONSIDERATIONS
- EVALUATION OF OPERATING CONDITIONS
- EVALUATION BOARD
- EVALUATION BOARD INSTRUCTIONS
- GENERAL OPERATING INSTRUCTIONS
- Hardware Preparation
- Clock Input, J25
- Three-State Control
- Programming
- Low-Pass Filter Testing
- Observing the Unfiltered IOUT1 and the Unfiltered IOUT2 DAC Signals
- Observing the Filtered IOUT1 and the Filtered IOUT2
- Observing the Filtered IOUT1 and the Filtered IOUT1
- Connecting the High Speed Comparator
- Single-Ended Configuration
- USING THE PROVIDED SOFTWARE
- SUPPORT
- OUTLINE DIMENSIONS
AD9852
Rev. E | Page 32 of 52
Table 9. Register Layout
1
AD9852 Register Layout Parallel
Address
(Hex)
Serial
Address
(Hex)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default
Value
(Hex)
00
01
0 Phase Adjust Register 1 <13:8> (Bits 15, 14 don’t care)
Phase Adjust Register 1 <7:0>
Phase 1 00
00
02
03
1 Phase Adjust Register 2 <13:8> (Bits 15, 14 don’t care)
Phase Adjust Register 2 <7:0>
Phase 2 00
00
04
05
06
07
08
09
2 Frequency Tuning Word 1 <47:40>
Frequency Tuning Word 1 <39:32>
Frequency Tuning Word 1 <31:24>
Frequency Tuning Word 1 <23:16>
Frequency Tuning Word 1 <15:8>
Frequency Tuning Word 1 <7:0>
Frequency 1 00
00
00
00
00
00
0A
0B
0C
0D
0E
0F
3 Frequency Tuning Word 2 <47:40>
Frequency Tuning Word 2 <39:32>
Frequency Tuning Word 2 <31:24>
Frequency Tuning Word 2 <23:16>
Frequency Tuning Word 2 <15:8>
Frequency Tuning Word 2 <7:0>
Frequency 2 00
00
00
00
00
00
10
11
12
13
14
15
Delta frequency word <47:40>
Delta frequency word <39:32>
Delta frequency word <31:24>
Delta frequency word <23:16>
Delta frequency word <15:8>
Delta frequency word <7:0>
00
00
00
00
00
00
16
17
18
19
5 Update clock <31:24>
Update clock <23:16>
Update clock <15:8>
Update clock <7:0>
00
00
00
00
1A
1B
1C
6 Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care)
Ramp rate clock <15:8>
Ramp rate clock <7:0>
00
00
00
1D 7
Don’t care
CR [31]
Don’t care
Don’t
care
Comp
PD
Reserved,
always
low
Control
DAC PD
DAC PD DIG PD 10
1E Don’t care PLL range
Bypass
PLL
Ref
Mult 4
Ref
Mult 3
Ref Mult 2
Ref
Mult 1
Ref Mult 0 64
1F CLR ACC1 CLR ACC2 Triangle
Don’t
care
Mode 2 Mode 1 Mode 0
Int/Ext
update clock
01
20 Don’t care
Bypass inv
sinc
OSK EN OSK INT Don’t care Don’t care LSB first
SDO active
CR [0]
20
21
22
8
Output shaped keying multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)
Output shaped keying multiplier <7:0>
00
00
23
24
9 Don’t care
Don’t care
00
00
25 A Output shaped keying ramp rate <7:0> 80
26
27
B Control DAC <11:8> (Bits 15, 14, 13, 12 don’t care)
Control DAC <7:0> (Data is required to be in twos complement format)
00
00
1
The shaded sections comprise the control register.