Datasheet

AD9852
Rev. E | Page 26 of 52
• Continue chirp by reversing the direction and returning to
the previous or another destination frequency in a linear or
user-directed manner. If this involves reducing the
frequency, a negative 48-bit delta frequency word (the
MSB is set to 1) must be loaded into Register 10 hex to
Register 15 hex. Any decreasing frequency step of the delta
frequency word requires the MSB to be set to logic high.
• Continue chirp by immediately returning to the beginning
frequency (F1) in a sawtooth fashion, and then repeating the
previous chirp process. In this case, an automatic repeating
chirp can be set up by using the 32-bit update clock to issue
the CLR ACC1 command at precise time intervals. Adjusting
the timing intervals or changing the delta frequency word
changes the chirp range. It is incumbent upon the user to
balance the chirp duration and frequency resolution to
achieve the proper frequency range.
BPSK (MODE 100)
Binary, biphase, or bipolar phase shift keying is a means to
rapidly select between two preprogrammed 14-bit output phase
offsets. The logic state of BPSK (Pin 29) controls the selection of
Phase Adjust Register 1 or Phase Adjust Register 2. When low,
BPSK selects Phase Adjust Register 1; when high, it selects
Phase Adjust Register 2.
Figure 45 illustrates phase changes
made to four cycles of an output carrier.
Basic BPSK Programming Steps
1. Program a carrier frequency into Frequency Tuning Word 1.
2. Program the appropriate 14-bit phase words into Phase Adjust
Register 1 and Phase Adjust Register 2.
3. Attach the BPSK data source to Pin 29.
4. Activate the I/O update clock when ready.
If higher-order PSK modulation is desired, the user can select
single-tone mode and program Phase Adjust Register 1 using
the serial or high speed parallel programming bus.
BPSK DATA
360
0
PHASE
MODE
FTW1
PHASE ADJUST 1
000 (DEFAULT)
0
PHASE ADJUST 2
100 (BPSK)
F1
270°
90°
I/O UD CLK
00634-045
Figure 45. BPSK Mode