Datasheet

AD9852
Rev. E | Page 25 of 52
CLR ACC2
F1
0
FREQUENCY
MODE
TW1
DPW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
I/O UD CLK
00634-043
Figure 43. Effect of CLR ACC2 in FM Chirp Mode
HOLD
F1
0
FREQUENCY
MODE
TW1
DFW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
F1
DELTA FREQUENCY WORD
RAMP RATE
I/O UD CLK
00634-044
Figure 44. Example of Hold Function
The 32-bit automatic I/O update counter can be used to
construct complex chirp or ramped FSK sequences. Because
this internal counter is synchronized with the AD9852 system
clock, it allows precisely timed program changes to be invoked.
For such changes, the user need only reprogram the desired
registers before the automatic I/O update clock is generated.
In chirp mode, the destination frequency is not directly speci-
fied. If the user fails to control the chirp, the DDS automatically
confines itself to the frequency range between dc and Nyquist.
Unless terminated by the user, the chirp continues until power
is removed.
When the chirp destination frequency is reached, the user can
choose any of the following actions:
• Stop at the destination frequency either by using the
HOLD pin or by loading all 0s into the delta frequency
word registers of the frequency accumulator (ACC1).
• Use the HOLD pin function to stop the chirp, and then ramp
down the output amplitude either by using the digital multi-
plier stages and the output shaped keying pin (Pin 30) or by
using the program register control (Address 21 hex to
Address 24 hex).
• Abruptly end the transmission with the CLR ACC2 bit.