CMOS 300 MSPS Complete DDS AD9852 FEATURES Frequency ramped FSK <25 ps rms total jitter in clock generator mode Automatic bidirectional frequency sweeping Sin(x)/x correction Simplified control interface 10 MHz serial 2-wire or 3-wire SPI-compatible 100 MHz parallel 8-bit programming 3.
AD9852 TABLE OF CONTENTS Features .............................................................................................. 1 Inverse Sinc Function ................................................................ 29 Applications....................................................................................... 1 REFCLK Multiplier .................................................................... 29 Functional Block Diagram ..............................................................
AD9852 REVISION HISTORY 5/07—Rev. D to Rev. E Changed AD9852ASQ to AD9852ASVZ ....................... Universal Changed AD9852AST to AD9852ASTZ......................... Universal Change to Features............................................................................1 Changes to Endnote 10 of Table 1...................................................7 Changes to Absolute Maximum Ratings........................................8 Added Thermal Resistance Section ..........................................
AD9852 GENERAL DESCRIPTION The AD9852 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable, agile synthesizer function. When referenced to an accurate clock source, the AD9852 generates a highly stable frequency-, phase-, and amplitude-programmable cosine output that can be used as an agile LO in communications, radar, and many other applications.
AD9852 SPECIFICATIONS VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASVZ, external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852ASTZ, unless otherwise noted. Table 1.
AD9852 Parameter Residual Phase Noise (AOUT = 5 MHz, External Clock = 30 MHz, REFCLK Multiplier Engaged at 10×) 1 kHz Offset 10 kHz Offset 100 kHz Offset (AOUT = 5 MHz, External Clock = 300 MHz, REFCLK Multiplier Bypassed) 1 kHz Offset 0 kHz Offset 100 kHz Offset PIPELINE DELAYS 3, 4, 5 DDS Core (Phase Accumulator and Phase-to-Amp Converter) Frequency Accumulator Inverse Sinc Filter Digital Multiplier DAC I/O Update Clock (Internal Mode) I/O Update Clock (External Mode) MASTER RESET DURATION COMPARATOR INPU
AD9852 Parameter PARALLEL I/O TIMING CHARACTERISTICS tASU (Address Setup Time to WR Signal Active) tADHW (Address Hold Time to WR Signal Inactive) tDSU (Data Setup Time to WR Signal Inactive) tDHD (Data Hold Time to WR Signal Inactive) tWRLOW (WR Signal Minimum Low Time) tWRHIGH (WR Signal Minimum High Time) tWR (Minimum WR Time) tADV (Address to Data Valid Time) tADHR (Address Hold Time to RD Signal Inactive) tRDLOV (RD Low to Output Valid) tRDHOZ (RD High to Data Three-State) SERIAL I/O TIMING CHARACTERIS
AD9852 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature VS Digital Inputs Digital Output Current Storage Temperature Operating Temperature Lead Temperature (Soldering, 10 sec) Maximum Clock Frequency (ASVZ) Maximum Clock Frequency (ASTZ) Rating 150°C 4V −0.
AD9852 PLL FILTER AGND NC DIFF CLK ENABLE AVDD AGND AGND REFCLK REFCLK S/P SELECT MASTER RESET DGND DVDD DVDD DGND DGND DGND DGND DVDD DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 D7 1 60 AVDD 59 AGND D5 3 58 NC D4 4 57 NC D3 5 56 DAC RSET D2 6 55 DACBP D1 7 54 AVDD 53 AGND 52 IOUT2 DVDD 10 51 IOUT2 DGND 11 50 AVDD DGND 12 49 IOUT1 NC 13 48 IOUT1 A5 14 47 AGND A4 15 46 AGND A3 16
AD9852 Pin Number 19 Mnemonic A0/SDIO 20 I/O UD CLK 21 WR/SCLK 22 RD/CS 29 FSK/BPSK/HOLD 30 OSK 31, 32, 37, 38, 44, 50, 54, 60, 65 33, 34, 39, 40, 41, 45, 46, 47, 53, 59, 62, 66, 67 36 AVDD 42 43 48 49 51 52 55 VINP VINN IOUT1 IOUT1 IOUT2 IOUT2 DACBP 56 DAC RSET 61 PLL FILTER 64 DIFF CLK ENABLE 68 REFCLK 69 REFCLK 70 S/P SELECT 71 MASTER RESET AGND VOUT Description Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0)/
AD9852 DVDD AVDD AVDD IOUT IOUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC Outputs COMPARATOR OUT VINP/ VINN B. Comparator Output AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. C. Comparator Input Figure 3. Equivalent Input and Output Circuits Rev. E | Page 11 of 52 DIGITAL IN D.
AD9852 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 15MHz/ STOP 150MHz –100 START 0Hz Figure 4. Wideband SFDR, 19.1 MHz –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 15MHz/ STOP 150MHz 00634-005 0 START 0Hz –100 START 0Hz Figure 5. Wideband SFDR, 39.
AD9852 0 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 CENTER 39.1MHz 100kHz/ SPAN 1MHz –100 CENTER 39.1MHz Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW, 300 MHz REFCLK with REFCLK Multiplier Bypassed 0 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 5kHz/ SPAN 50kHz 00634-011 0 CENTER 39.1MHz SPAN 1MHz Figure 13. Narrow-Band SFDR, 39.
AD9852 Figure 18 and Figure 19 show the residual phase noise performance of the AD9852 when operating with a 300 MHz reference clock with the REFCLK multiplier bypassed vs. a 30 MHz reference clock with the REFCLK multiplier enabled at 10×. 0 –90 –10 –100 –30 –40 –50 –60 –70 –80 AOUT = 80MHz –110 –120 –130 –140 –150 AOUT = 5MHz –100 50kHz/ CENTER 112.469MHz SPAN 500kHz 00634-016 –90 –160 10 Figure 16. A Slight Change in Tuning Word Yields Dramatically Better Results; 112.
AD9852 1200 AMPLITUDE (mV p-p) 1000 RISE TIME 1.04ns JITTER [10.6ps RMS] 800 600 400 MINIMUM COMPARATOR INPUT DRIVE VCM = 0.5V 200 232mV/DIV +33ps 50Ω INPUT 0 0 Figure 22. Typical Comparator Output Jitter, 40 MHz AOUT, 300 MHz REFCLK with REFCLK Multiplier Bypassed M 500ps CH1 980mV 00634-023 C1 FALL 1.286ns 500mVΩ 200 300 FREQUENCY (MHz) 400 Figure 24. Comparator Toggle Voltage Requirement REF1 RISE 1.174ns CH1 100 Figure 23. Comparator Rise/Fall Times Rev.
AD9852 TYPICAL APPLICATIONS RF/IF INPUT LOW-PASS FILTER AD9852 COS 00634-025 REFCLK BASEBAND Figure 25. Synthesized LO Application for the AD9852 8 I I/Q MIXER AND LOW-PASS FILTER DUAL 8-/10-BIT ADC Q Rx BASEBAND DIGITAL DATA OUT DIGITAL DEMODULATOR 8 VCA AGC ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/ SYMBOL/PN RATE ADC ENCODE REFERENCE CLOCK 48 CHIP/SYMBOL/PN RATE DATA 00634-026 AD9852 CLOCK GENERATOR Figure 26.
AD9852 REFERENCE CLOCK DDS FILTER PHASE LOOP COMPARATOR FILTER TUNING WORD RF FREQUENCY OUT VCO 00634-029 AD9852 DIVIDE-BY-N Figure 29. Agile High Frequency Synthesizer DIFFERENTIAL TRANSFORMER-COUPLED OUTPUT IOUT FILTER 50Ω AD9852 DDS IOUT 50Ω 1:1 TRANSFORMER THAT IS, Mini-Circuits® T1-1T 00634-030 REFERENCE CLOCK Figure 30.
AD9852 MODES OF OPERATION There are five programmable modes of operation of the AD9852. Selecting a mode requires that three bits in the control register (Parallel Address 1F hex) be programmed as shown in Table 6. As with all Analog Devices DDS devices, the value of the frequency tuning word is determined using the following equation: Table 6. Mode Selection Table where: N is the phase accumulator resolution (48 bits in this instance). Desired Output Frequency is expressed in hertz.
AD9852 Table 7. Function Availability vs.
AD9852 F2 FREQUENCY F1 0 000 (DEFAULT) 010 (RAMPED FSK) TW1 0 F1 TW2 0 F2 MODE REQUIRES A POSITIVE TWOS COMPLEMENT VALUE DFW RAMP RATE 00634-034 I/O UD CLK FSK DATA (PIN 29) Figure 34. Ramped FSK Mode (Start at F1) F2 FREQUENCY F1 0 MODE 000 (DEFAULT) 010 (RAMPED FSK) TW1 0 F1 TW2 0 F2 00634-035 I/O UD CLK FSK DATA (PIN 29) Figure 35. Ramped FSK Mode (Start at F2) The purpose of ramped FSK is to provide better bandwidth containment than can be achieved using traditional FSK.
AD9852 Figure 36. The ramp rate clock determines the amount of time spent at each intermediate frequency between F1 and F2. Parallel Register Address 10 hex to Parallel Register Address 15 hex comprise the 48-bit, twos complement delta frequency word registers. This 48-bit word is accumulated (added to the accumulator’s output) every time it receives a clock pulse from the ramp rate counter.
AD9852 Additional flexibility in the ramped FSK mode is provided by the AD9852’s ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp rate counter at any time during the ramping from F1 to F2 or vice versa. To create these nonlinear frequency changes, it is necessary to combine several linear ramps with different slopes in a piecewise fashion.
AD9852 OUT PHASE ACCUMULATOR ADDER FREQUENCY ACCUMULATOR 48-BIT DELTA FREQUENCY WORD (TWOS COMPLEMENT) CLR ACC1 FREQUENCY TUNING WORD 1 20-BIT RAMP RATE CLOCK SYSTEM CLOCK 00634-040 HOLD CLR ACC2 Figure 40. FM Chirp Components FREQUENCY F1 0 MODE TW1 000 (DEFAULT) 010 (RAMPED FSK) 0 F1 DFW 00634-041 RAMP RATE I/O UD CLK Figure 41. Example of a Nonlinear Chirp Basic FM Chirp Programming Steps 1.
AD9852 supplied or internally generated. See the Internal and External Update Clock section for a discussion of the I/O update. Alternatively, the CLR ACC2 control bit (Register Address 1F hex) is available to clear both the frequency accumulator (ACC1) and the phase accumulator (ACC2). When this bit is set high, the output of the phase accumulator results in 0 Hz output from the DDS. As long as this bit is set high, the frequency and phase accumulators are cleared, resulting in 0 Hz output.
AD9852 FREQUENCY F1 0 MODE 000 (DEFAULT) 011 (CHIRP) 0 TW1 DPW RAMP RATE 00634-043 CLR ACC2 I/O UD CLK Figure 43. Effect of CLR ACC2 in FM Chirp Mode FREQUENCY F1 0 MODE TW1 000 (DEFAULT) 011 (CHIRP) 0 F1 DELTA FREQUENCY WORD DFW RAMP RATE RAMP RATE 00634-044 HOLD I/O UD CLK Figure 44. Example of Hold Function The 32-bit automatic I/O update counter can be used to construct complex chirp or ramped FSK sequences.
AD9852 • Continue chirp by reversing the direction and returning to the previous or another destination frequency in a linear or user-directed manner. If this involves reducing the frequency, a negative 48-bit delta frequency word (the MSB is set to 1) must be loaded into Register 10 hex to Register 15 hex. Any decreasing frequency step of the delta frequency word requires the MSB to be set to logic high.
AD9852 USING THE AD9852 INTERNAL AND EXTERNAL UPDATE CLOCK ON/OFF OUTPUT SHAPED KEYING (OSK) The update clock function is composed of a bidirectional I/O pin (Pin 20) and a programmable 32-bit down-counter. In order for programming changes to be transferred from the I/O buffer registers to the active core of the DDS, a clock signal (low-to-high edge) must be externally supplied to Pin 20 or internally generated by the 32-bit update clock.
AD9852 A total of 4096 output pulses is required to advance the 12-bit up-counter from zero scale to full scale. Therefore, the minimum output shaped keying ramp time for a 100 MHz system clock is The two fixed elements of the transition time are the period of the system clock (which drives the ramp rate counter) and the number of amplitude steps (4096).
AD9852 4.0 COSINE DAC 3.5 3.0 The cosine output of the DDS drives the cosine DAC (300 MSPS maximum). Its maximum output amplitude is set by the DAC RSET resistor at Pin 56. This is a current-output DAC with a full-scale maximum output of 20 mA; however, a nominal 10 mA output current provides best spurious-free dynamic range (SFDR) performance. The value of RSET is 39.93/IOUT, where IOUT is expressed in amps. DAC output compliance specifications limit the maximum voltage developed at the outputs to −0.
AD9852 PLL Filter The PLL FILTER pin (Pin 61) provides the connection for the external zero-compensation network of the PLL loop filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF capacitor. The other side of the network should be connected as close as possible to Pin 60 (AVDD). For optimum phase noise performance, the clock multiplier can be bypassed by setting the bypass PLL bit in Control Register Address 1E hex.
AD9852 PROGRAMMING THE AD9852 The AD9852 Register Layout table (Table 9) contains information for programming a chip for a desired functionality. Although many applications require very little programming to configure the AD9852, some use all 12 accessible register banks. The AD9852 supports an 8-bit parallel I/O operation or an SPIcompatible serial I/O operation. All accessible registers can be written and read back in either I/O operating mode. S/P SELECT (Pin 70) is used to configure the I/O mode.
AD9852 Table 9.
AD9852 A<5:0> A1 A2 A3 D<7:0> D1 D2 D3 RD tRDLOV tAHD tADV SPECIFICATION VALUE DESCRIPTION tADV tAHD tRDLOV tRDHOZ 15ns 5ns 15ns 10ns ADDRESS TO DATA VALID TIME (MAXIMUM) ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM) RD LOW TO OUTPUT VALID (MAXIMUM) RD HIGH TO DATA THREE-STATE (MAXIMUM) 00634-049 tRDHOZ Figure 49.
AD9852 GENERAL OPERATION OF THE SERIAL INTERFACE B Register Name Phase Offset Tuning Word Register 1 Phase Offset Tuning Word Register 2 Frequency Tuning Word 1 Frequency Tuning Word 2 Delta frequency register Update clock rate register Ramp rate clock register Control register Digital multiplier register On/off output shaped keying ramp rate register Control DAC register CS INSTRUCTION BYTE DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 SDIO INSTRUCTION CYCLE DATA TRANSFER Figure 51.
AD9852 SERIAL INTERFACE PORT PIN DESCRIPTIONS Table 12. Pin SCLK CS SDIO SDO IO RESET Description Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 and to run the internal state machines. The SCLK maximum frequency is 10 MHz. Chip Select (Pin 22). Active low input that allows more than one device on the same serial communication line. The SDO and SDIO pins go to a high impedance state when this input is high.
AD9852 CONTROL REGISTER DESCRIPTIONS The control register is located at Address 1D hex to Address 20 hex (shown in the shaded portion of Table 9). It is composed of 32 bits. Bit 31 is located at the top left position, and Bit 0 is located in the lower right position of the shaded area of Table 9. The register has been subdivided into bits to make it easier to locate the information associated with specific control categories. Table 13.
AD9852 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I7 I6 I5 I4 I3 I2 I1 D7 I0 D6 D5 D4 D3 D2 D1 00634-055 SCLK D0 Figure 55. Serial Port Write Timing Clock Stall Low DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK I7 I6 I5 I4 I3 I2 I1 I0 DON’T CARE DO6 DO7 SDO DO5 DO4 DO3 DO2 DO1 00634-056 SDIO DO0 Figure 56.
AD9852 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9852 is a multifunctional, high speed device that targets a wide variety of synthesizer and agile clock applications. The numerous innovative features contained in the device each consume incremental power. If enabled in combination, the safe thermal operating conditions of the device may be exceeded.
AD9852 inverse sinc filter, both DACs, and the on-board comparator are enabled. Basic configuration means the output scaling multipliers, the inverse sinc filter, the control DAC, and the on-board comparator are disabled. 500 INVERSE SINC FILTER 450 Figure 60 shows the approximate current consumed by each of the four functions.
AD9852 EVALUATION OF OPERATING CONDITIONS The first step in applying the AD9852 is to select the internal clock frequency. Clock frequency selections greater than 200 MHz require use of the thermally enhanced package (AD9852ASVZ); clock frequency selections equal to or less than 200 MHz may allow use of the standard (nonthermally enhanced) plastic surface-mount package, but more information is needed to make this determination. power dissipation limit of 4.1 W and 1.
AD9852 EVALUATION BOARD An evaluation board is available that supports the AD9852 DDS device. This evaluation board consists of a PCB, software, and documentation to facilitate bench analysis of the performance of the AD9852 device. It is recommended that users of the AD9852 familiarize themselves with the operation and performance capabilities of the device by using the evaluation board.
AD9852 Programming If a PC and Analog Devices software are not used to program the AD9852, the W9, W11, W12, W13, W14, and W15 headers should be opened (shorting jumpers removed). This effectively detaches the PC interface and allows J10 (the 40-pin header) and J1 to assume control without bus contention. Input signals on J10 and J1 going to the AD9852 should be 3.3 V CMOS logic levels.
AD9852 This step reroutes the filtered signals from the output connectors (J6 and J7) to the 100 Ω configured comparator inputs. This sets up the comparator for differential input without affecting the comparator output duty cycle, which should be approximately 50% for the complementary filtered output configuration. Several numerical entries, such as frequency and phase information, require pressing ENTER to register this information.
AD9852 Table 15.
AD9852 Item 24 Qty 1 Reference Designator TB1 Device TB4 Package 4-position terminal Value N/A Min Tol N/A 25 26 1 1 U1 U2 AD9852 74HC125D SV-80 14 SOIC N/A N/A N/A N/A 27 1 U3 8 SOIC N/A N/A Analog Devices, Inc. Texas Instruments Incorporated ON Semiconductor 8 SOIC N/A N/A ON Semiconductor 14 SOIC N/A N/A TSW-103-07-S-S Manufacturer Wieland Electric, Inc. Manufacturer Part No. Plug: 25.602.2453.0; terminal strip: Z5.530.3425.
DGND1 3 4 5 6 7 8 9 10 11 D5 D4 D3 D2 D1 D0 DVDD DVDD ADDR3 A2/IO RESET A1/SDO 15 16 17 18 19 20 A4 A3 A2/IO RESET A1/SDO A0/SDIO I/O UD CLK GND J10 ADDR5 14 A5 UPDCLK A0/SDIO ADDR4 NC 13 DGND7 AVDD PMODE TOP VIEW (Not to Scale) AD9852 U1 CLKVDD VOUT NC2 DGND8 DVDD4 DVDD DVDD RD/CS WR/SCLK 1 FDATA 1 4 3 2 GND VCC DVDD C20 0.1μF C6 10μF C19 0.1μF C18 0.1μF C17 0.1μF W7 C16 0.1μF J25 C12 0.1μF 1 GND L6 82nH Y1 3.
Figure 62. Evaluation Board Schematic Rev.
00634-067 AD9852 00634-068 Figure 63. Assembly Drawing Figure 64. Top Routing Layer, Layer 1 Rev.
00634-070 AD9852 00634-069 Figure 65. Ground Plane Layer, Layer 2 Figure 66. Power Plane Layer, Layer 3 Rev.
00634-071 AD9852 Figure 67. Bottom Routing Layer, Layer 4 Rev.
AD9852 OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 0.75 0.60 0.45 14.20 14.00 SQ 13.80 1.20 MAX 80 61 1 61 60 80 1 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 0° MIN 1.05 1.00 0.95 0.15 0.05 9.50 SQ SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 20 41 21 40 BOTTOM VIEW (PINS UP) 41 20 21 40 VIEW A 0.65 BSC LEAD PITCH 0.27 0.22 0.17 VIEW A 091506-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AEC-HD Figure 68.
AD9852 ORDERING GUIDE Model AD9852ASVZ 1 AD9852AST AD9852ASTZ1 AD9852/PCB 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Z = RoHS Compliant Part. ©2002–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00634-0-5/07(E) Rev.
