Datasheet

AD9851
–8
–
FREQUENCY OFFSET – Hz
–155
100
MAGNITUDE – –dBc/Hz
1k 10k 100k
–145
–140
–135
–130
–125
–120
AD9851 RESIDUAL PHASE NOISE
–150
TPC 11. Output Residual Phase Noise (5.2 MHz A
OUT
), 6
OUT
), 6
OUT

REFCLK Multiplier Disabled, System Clock = 180 MHz, Ref-
erence Clock = 180 MHz
SYSTEM CLOCK FREQUENCY – MHz
45
10
SFDR – –dBc
20 40 60 80 100 120 140 160 180
50
55
60
65
70
75
V
S
= +3.3V
V
S
= +5V
FUNDAMENTAL OUTPUT =
SYSTEM CLOCK/3
TPC 12. Spurious-free dynamic range (SFDR) is gen er al ly
a function of the DAC analog output frequency. An a log
output frequencies of 1/3 the system clock rate are consid-
ered worst case. Plotted below are typical worst case SFDR
numbers for various system clock rates.
1
Ch1 100mV
T
[ ]
Tek Stop 2.50GS/s 22 Acgs
 : 2.0ns
@ : 105.2ns
C1 Rise
2.03ns
M 20.0ns Ch 1 252mV
D 5.00ns Runs After
TPC 13. Comparator Rise Time, 15 pF Load
1
Ch1 100mV
T
[ ]
Tek Stop 2.50GS/s 2227 Acgs
 : 2.3ns
@ : 103.6ns
C1 Fall
2.33ns
M 20.0ns Ch 1 252mV
D 5.00ns Runs After
TPC 14. Comparator Fall Time, 15 pF Load
ANALOG OUTPUT FREQUENCY – MHz
30
10
SUPPLY CURRENT – mA
20 30 40 50 600 70
50
70
80
90
110
120
V
S
= +3.3V
V
S
= +5V
100
60
40
TPC 15. Supply current variation with analog
output frequency at 180 MHz system clock (upper
trace) and 125 MHz system clock (lower trace)
SYSTEM CLOCK – MHz
0
140
SUPPLY CURRENT – mA
20 40 60 10080 1200
20
40
60
80
100
120
V
S
= +3.3V
V
S
= +5V
160 180
TPC 16. Supply current variation with system
clock frequency
REV. D