Datasheet

AD9851
–3
–
Test
AD9851BRS
Parameter
Temp
Level
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
4
t
WH
, t
WL
(W_CLK Min Pulse Width High/Low)
WL
(W_CLK Min Pulse Width High/Low)
WL
Full
IV
3.5
ns
t
DS
, t
DH
(Data to W_CLK Setup and Hold Times)
Full
IV
3.5
ns
t
FH
, t
FL
(FQ_UD Min Pulse Width High/Low)
FL
(FQ_UD Min Pulse Width High/Low)
FL
Full
IV
7
ns
t
CD
(REFCLK Delay After FQ_UD)
5
Full
IV
3.5
ns
t
FD
(FQ_UD Min Delay After W_CLK)
Full
IV
7
ns
t
CF
(Out put Latency from FQ_UD)
Frequency Change
Full
IV
18
SYSCLK
Cycles
Phase Change
Full
IV
13
SYSCLK
Cycles
t
RH
(CLKIN Delay After RESET Rising Edge)
Full
IV
3.5
ns
t
RL
(RESET Falling Edge After CLKIN)
RL
(RESET Falling Edge After CLKIN)
RL
Full
IV
3.5
ns
t
RR
(Recovery from RESET)
RR
(Recovery from RESET)
RR
Full
IV
2
SYSCLK
Cycles
t
RS
(Min i mum RE SET Width)
Full
IV
5
SYSCLK
Cycles
t
OL
(RESET Output Latency)
OL
(RESET Output Latency)
OL
Full
IV
13
SYSCLK
Cycles
Wake-Up Time from Power-Down Mode
6
25°C
V
5
µs
CMOS LOGIC INPUTS
Logic 1 Voltage, 5 V Supply
25°C
I
3.5
V
Logic 1 Voltage, 3.3 V Supply
25°C
IV
2.4
V
Logic 1 Voltage, 2.7 V Supply
25°C
IV
2.0
V
Logic 0 Voltage
25°C
IV
0.8
V
Logic 1 Current
25°C
I
12
µA
Logic 0 Current
25°C
I
12
µA
Rise/Fall Time
25°C
IV
100
ns
Input Capacitance
25°C
V
3
pF
POWER SUPPLY
V
S
6
Current @:
62.5 MHz Clock, 2.7 V Supply
25°C
VI
30
35
mA
100 MHz Clock, 2.7 V Supply
25°C
VI
40
50
mA
62.5 MHz Clock, 3.3 V Supply
25°C
VI
35
45
mA
125 MHz Clock, 3.3 V Supply
25°C
VI
55
70
mA
62.5 MHz Clock, 5 V Supply
25°C
VI
50
65
mA
125 MHz Clock, 5 V Supply
25°C
VI
70
90
mA
180 MHz Clock, 5 V Supply
25°C
VI
110
130
mA
Power Dissipation @ :
62.5 MHz Clock, 5 V Supply
25°C
VI
250
325
mW
62.5 MHz Clock, 3.3 V Supply
25°C
VI
115
150
mW
62.5 MHz Clock, 2.7 V Supply
25°C
VI
85
95
mW
100 MHz Clock, 2.7 V Supply
25°C
VI
110
135
mW
125 MHz Clock, 5 V Supply
25°C
VI
365
450
mW
125 MHz Clock, 3.3 V Supply
25°C
VI
180
230
mW
180 MHz Clock, 5 V Supply
25°C
VI
555
650
mW
P
DISS
Power-Down Mode @:
5 V Supply
25°C
VI
17
55
mW
2.7 V Supply
25°C
VI
4
20
mW
NOTES
1
+V
S
collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD. Voltages applied to these pins should be of the same po ten tial.
2
Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This speci es the p-p signal level and dc offset needed when the
clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.
3
The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more output
jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic signals (spur’s,
noise), slower slew rate, and low comparator overdrive.
4
Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those
functions. In the absence of a reference clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable until a refer-
ence clock is restored. Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the ex ter nal reference clock to
ensure proper timing.
5
Not applicable when 6

REFCLK Multiplier is engaged.
6
Assumes no capacitive load on DACBP (Pin 17).
Speci cations subject to change without notice.
REV. D