Datasheet

AD9851
–15
–
Results of Reset, Figure 14
–
Phase accumulator zeroed such that the output = 0 Hz (dc)
–
Phase offset register set to 0 such that DAC IOUT = full-scale
output and IOUTB = zero mA output
–
Internal programming address pointer reset to W0
–
Power-down bit reset to 0 (power-down disabled)
–
40-bit data input register is NOT cleared
–
6

reference clock multiplier is disabled
–
Parallel programming mode selected by default
XXXXX10X
FQ UD
W CLK
SYSCLK
DAC
STROBE
DATA (W0)
INTERNAL CLOCKS
DISABLED
Figure 15. Parallel Load Power-Down Sequence/
Internal Operation
XXXXX00X
FQ UD
W CLK
DATA (W0)
INTERNAL CLOCKS
ENABLED
SYSCLK
Figure 16. Parallel Load Power-Up Sequence (to
Recover from Power-Down)/Internal Operation
Entry to the serial mode, see Figure 17, is via the parallel mode,
which is se lect ed by default after a RESET is asserted. One needs
only to program the  rst eight bits (word W0) with the se quence
xxxxx011 as shown in Figure 17 to change from par al lel to serial
mode. The W0 programming word may be sent over the 8-bit
data bus or hardwired as shown in Figure 18. After serial mode
is achieved, the user must follow the programming se quence of
Figure 19.
XXXXX011
FQ UD
W CLK
DATA (W0)
ENABLE
SERIAL MODE
Figure 17. Serial Load Enable Sequence
Note: After serial mode is invoked, it is best to immediately write
a valid 40-bit serial word (see Figure 19), even if it is all zeros,
fol lowed by a FQ_UD rising edge to  ush the residual data left in
the DDS core. A valid 40-bit serial word is any word where W33
is Logic 0.
28
27
26
25
1
2
3
4
AD9851
D3
D2
D1
D0
D4
D5
D6
D7
10k
+V
SUPPLY
Figure 18. Hardwired xxxxx011 Con guration for
Serial Load Enable Word W0 in Figure 17
SYSCLK
RESET
A
OUT
t
RH
t
RL
COS (0

)
SYMBOL DEFINITION MIN SPEC
t
RH
CLK DELAY AFTER RESET RISING EDGE 3.5ns*
t
RL
RESET FALLING EDGE AFTER CLK 3.5ns*
t
RR
RECOVERY FROM RESET 2 SYSCLK CYCLES
t
RS
MINIMUM RESET WIDTH 5 SYSCLK CYCLES
t
OL
RESET OUTPUT LATENCY 13 SYSCLK CYCLES
*SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED
t
RR
NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME
NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT
HAVE TO BE SYNCHRONOUS TO THE SYSCLK IF THE MINIMAL TIME IS NOT REQUIRED.
t
RS
t
OL
Figure 14. Master Reset Timing Sequence
Note: The timing diagram above shows the minimal amount of reset time needed before writing to the device. However, the master reset does not have to be synchronous to
the SYSCLK if the minimal time is not required.
REV. D