Datasheet

AD9851
–12
–
THEORY OF OPERATION AND APPLICATION
The AD9851 uses direct digital synthesis (DDS) technology,
in the form of a nu mer i cal ly controlled oscillator (NCO), to
gen er ate a frequency/phase-agile sine wave. The digital sine
wave is converted to analog form via an internal 10-bit high
speed D/A converter. An on-board high speed comparator
is provided to translate the analog sine wave into a low-jitter
TTL/CMOS-compatible output square wave. DDS technol-
ogy is an in no va tive circuit architecture that allows fast and
precise ma nip u la tion of its output word, under full digital con-
trol. DDS also enables very high resolution in the incremental
se lec tion of output fre quen cy. The AD9851 allows an output
fre quen cy resolution of approximately 0.04 Hz at an 180 MSPS
clock rate with the option of directly using the reference clock or
by engaging the 6

REFCLK multiplier. The AD9851’s out-
put waveform is phase-con tin u ous from one output fre quen cy
change to another.
The basic functional block diagram and signal  ow of the
AD9851 con gured as a clock generator is shown in Figure 11.
The DDS circuitry is basically a digital frequency divider func tion
whose incremental resolution is determined by the fre quen cy of
the system clock, and N (number of bits in the tuning word). The
phase accumulator is a variable-modulus counter that in cre ments
the number stored in it each time it receives a clock pulse. When
the counter reaches full-scale it wraps around, making the phase
accumulator’s output phase-con tin u ous. The frequency tuning
word sets the modulus of the counter, which effectively determines
the size of the increment (

Phase) that will be added to the value
in the phase accumulator on the next clock pulse. The larger
the added increment, the faster the accumulator wraps around,
which results in a higher output frequency.
The AD9851 uses an innovative and proprietary angle ro ta tion
algorithm that mathematically converts the 14-bit trun cat ed
value of the 32-bit phase accumulator to the 10-bit quan tized
amplitude that is passed to the DAC. This unique algorithm uses a
much-reduced ROM look-up table and DSP to perform this func-
tion. This contributes to the small size and low power dissipation of
the AD9851.
The relationship between the output frequency, system clock, and
tuning word of the AD9851 is determined by the ex pres sion:
f
OUT
f
OUT
f
= (
OUT
= (
OUT

= (  = (
Phase

System Clock)/
2
32
where

Phase
= decimal value of 32-bit frequency tuning word.
System Clock
= direct input reference clock (in MHz) or 6

the
input clock (in MHz) if the 6

REFCLK multiplier is engaged.
f
OUT
f
OUT
f
= frequency of the output signal in MHz.
OUT
= frequency of the output signal in MHz.
OUT
The digital sine wave output of the DDS core drives the in ter nal
high speed 10-bit D/A converter that will construct the sine wave
in analog form. This DAC has been op ti mized for dy nam ic per-
formance and low glitch energy, which results in the low spurious
and jitter performance of the AD9851. The DAC can be operated
in either the single-ended (Figures 2 and 8) or dif fer en tial output
con guration (Figures 9 and 10). DAC out put current and R
SET
values are determined using the fol low ing expressions:
I
OUT
I
OUT
I
= 39.93/
OUT
= 39.93/
OUT
R
SET
R
SET
= 39.93/
SET
= 39.93/
SET
I
OUT
I
OUT
I
Since the output of the AD9851 is a sampled signal, its output
spectrum follows the Nyquist sampling theorem. Speci cally,
its output spectrum contains the fundamental plus aliased sig-
nals (images) that occur at integer multiples of the system clock
frequency ± the selected output frequency. A graphical rep re -
sen ta tion of the sampled spectrum, with aliased images, is shown
in Figure 12. Normal usable bandwidth is considered to extend
from dc to 1/2 the system clock.
CLOCK
OUT
AMPLITUDE/SINE
CONV ALGORITHM
PHASE
ACCUMULATOR
DDS CIRCUITRY
D/A
CONVERTER
LP COMPARATOR
N
REFERENCE
CLOCK
TUNING WORD SPECIFIES
OUTPUT FREQUENCY AS A
FRACTION OF REF CLOCK
FREQUENCY
IN DIGITAL
DOMAIN
Figure 11. Basic DDS Block Diagram and Signal Flow of AD9851
120MHz
2ND IMAGE
F
OUT
F
C
+F
O
2F
C
–F
O
2F
C
+F
O
3F
C
–F
O
180MHz
3RD IMAGE
220MHz
4TH IMAGE
280MHz
5TH IMAGE
80MHz
1ST IMAGE
20MHz0Hz
(DC)
F
C
F
C
–F
O
SIN (X)/ ENVELOPE
 = ()F/F
C
100MHz
SYSTEM CLOCK FREQUENCY
SIGNAL AMPLITUDE
Figure 12. Output Spectrum of a Sampled Sin(x)/x Signal
REV. D