Datasheet

AD9851
–11
–
REF
CLOCK
90
PHASE
DIFFERENCE
8-BIT DATA BUS
FQ UD
RESET
W CLK
AD9851
#2
IOUT
AD9851
#1
W CLK
FQ UD
RESET
IOUT
RESET
FQ UD
RESET
FQ UD
W CLK #2
W CLK #1
MICROPROCESSOR
OR
MICROCONTROLLER
W CLK #2
W CLK #1
Figure 7. Application Showing Synchronization of
Two AD9851 DDSs to Form a Quadrature Oscillator
After a common RESET command is issued, separate W_CLKs
allow independent programming of each AD9851 40-bit input reg-
ister via the 8-bit data bus or serial input pin. A common FQ_UD
pulse is issued after programming is completed to simultaneously
engage both oscillators at their speci ed fre quen cy and phase.
AD9851
IOUT
30MHz
CLOCK
BANDPASS
FILTER
5050
FUNDAMENTAL
F
CLK
IMAGE
F
C
– F
O
IMAGE
F
C
+ F
O
AMPLITUDE
60 120 180 240
FREQUENCY – MHz
240
FREQUENCY – MHz
IMAGE
F
C
+ F
O
BANDPASS
FILTER
AMPLITUDE
 6
AMPLIFIER
240MHz
AD9851
SPECTRUM
FINAL OUTPUT
SPECTRUM
Figure 8. Deriving a High Frequency Output Signal
from the AD9851 by Using an Alias or Image Signal
The differential DAC output connection in Figure 9 enables
reduction of com mon-mode signals and allows highly reactive
 lters to be driv en without a  lter input termination resistor (see
above single-ended example, Figure 8). A 6 dB power advantage
is obtained at the  lter output as compared with the single-ended
example, since the  lter need not be doubly terminated.
REFERENCE
CLOCK
FILTER
DIFFERENTIAL
TRANSFORMER COUPLED
OUTPUT
50
1:1 TRANSFORMER
i.e., MINI-CIRCUITS T1–1T
50
AD9851
DDS
21
20
Figure 9. Differential DAC Output Connection for
Re duc tion of Common-Mode Signals
The AD9851 R
SET
input is driven by an external DAC (Figure 10)
SET
input is driven by an external DAC (Figure 10)
SET
to provide amplitude modulation or  xed, digital am pli tude con trol
of the DAC output current. Full description of this ap pli ca tion is
found as a Technical Note in the AD9851 data sheet under Related
In for ma tion. An Analog Devices' application note for the AD9850,
AN-423, describes another method of am pli tude control using
an en hance ment mode MOSFET that is equally applicable to
the AD9851.
NOTE: If the 6

REFCLK multiplier of the AD9851 is en gaged,
the 125 MHz clock ing source shown in Figure 10 can be re duced
by a factor of six.
AD9851
DDS
DIFFERENTIAL
TRANSFORMER COUPLED
OUTPUT
50
1:1 TRANSFORMER
50
IOUT
IOUT
R
SET
+5V
21
20
12
9
4k
200
330
+5V
20mA
MAX
10-BIT DAC
AD9731
+5V
–5V
125MHz
10 BITS
DATA
GENERATOR
e.g., DG-2020
COMPUTER
CONTROL
DATA
Figure 10. The AD9851 RSET Input Being Driven by an External DAC
REV. D