Datasheet

AD9850BRS
Parameter Temp Test Level Min Typ Max Unit
CMOS LOGIC INPUTS (Including CLKIN)
Logic 1 Voltage, 5 V Supply 25°CI 3.5 V
Logic 1 Voltage, 3.3 V Supply 25°CIV 2.4 V
Logic 0 Voltage 25°CIV 0.8 V
Logic 1 Current 25°CI 12µA
Logic 0 Current 25°CI 12µA
Input Capacitance 25°CV 3 pF
POWER SUPPLY (A
OUT
= 1/3 CLKIN)
+V
S
Current @
62.5 MHz Clock, 3.3 V Supply Full VI 30 48 mA
110 MHz Clock, 3.3 V Supply Full VI 47 60 mA
62.5 MHz Clock, 5 V Supply Full VI 44 64 mA
125 MHz Clock, 5 V Supply Full VI 76 96 mA
P
DISS
@
62.5 MHz Clock, 3.3 V Supply Full VI 100 160 mW
110 MHz Clock, 3.3 V Supply Full VI 155 200 mW
62.5 MHz Clock, 5 V Supply Full VI 220 320 mW
125 MHz Clock, 5 V Supply Full VI 380 480 mW
P
DISS
Power-Down Mode
5 V Supply Full V 30 mW
3.3 V Supply Full V 10 mW
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
TIMING CHARACTERISTICS*
AD9850BRS
Parameter Temp Test Level Min Typ Max Unit
t
DS
(Data Setup Time) Full IV 3.5 ns
t
DH
(Data Hold Time) Full IV 3.5 ns
t
WH
(W_CLK Minimum Pulse Width High) Full IV 3.5 ns
t
WL
(W_CLK Minimum Pulse Width Low) Full IV 3.5 ns
t
WD
(W_CLK Delay after FQ_UD) Full IV 7.0 ns
t
CD
(CLKIN Delay after FQ_UD) Full IV 3.5 ns
t
FH
(FQ_UD High) Full IV 7.0 ns
t
FL
(FQ_UD Low) Full IV 7.0 ns
t
CF
(Output Latency from FQ_UD)
Frequency Change Full IV 18 CLKIN Cycles
Phase Change Full IV 13 CLKIN Cycles
t
FD
(FQ_UD Minimum Delay after W_CLK) Full IV 7.0 ns
t
RH
(CLKIN Delay after RESET Rising Edge) Full IV 3.5 ns
t
RL
(RESET Falling Edge after CLKIN) Full IV 3.5 ns
t
RS
(Minimum RESET Width) Full IV 5 CLKIN Cycles
t
OL
(RESET Output Latency) Full IV 13 CLKIN Cycles
t
RR
(Recovery from RESET) Full IV 2 CLKIN Cycles
Wake-Up Time from Power-Down Mode 25°CV 5 µs
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
(V
S
= 5 V ⴞ 5% except as noted, R
SET
= 3.9 k⍀)
REV. H
–3–
AD9850