Datasheet

AD9850
–12–
REV. H
XXXXX011
DATA (W0)
(PARALLEL)
W
CLK
FQ
UD
NOTE: W32 AND W33 SHOULD ALWAYS BE SET TO 0.
DATA (SERIAL)
REQUIRED TO RESET CONTROL REGISTERS
NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARDWIRE PIN 2 AT 0, PIN 3 AT 1, AND PIN 4 AT 1
(SEE FIGURE 11).
W32 = 0 W33 = 0
ENABLE SERIAL MODE
LOAD 40-BIT SERIAL WORD
Figure 10. Serial Load Enable Sequence
+V
SUPPLY
3
4
2
AD9850BRS
Figure 11. Pins 2 to 4 Connection for Default Serial Mode Operation
DATA –
W
CLK
FQ
UD
W0 W1 W2 W3 W39
40 W CLK CYCLES
Figure 12. Serial Load Frequency/Phase Update Sequence
Table IV. 40-Bit Serial Load Word Function Assignment
W0 Freq-b0 (LSB)
W1 Freq-b1
W2 Freq-b2
W3 Freq-b3
W4 Freq-b4
W5 Freq-b5
W6 Freq-b6
W7 Freq-b7
W8 Freq-b8
W9 Freq-b9
W10 Freq-b10
W11 Freq-b11
W12 Freq-b12
W13 Freq-b13
W28 Freq-b28
W29 Freq-b29
W30 Freq-b30
W31 Freq-b31 (MSB)
W32 Control
W33 Control
W34 Power-Down
W35 Phase-b0 (LSB)
W36 Phase-b1
W37 Phase-b2
W38 Phase-b3
W39 Phase-b4 (MSB)
W14 Freq-b14
W15 Freq-b15
W16 Freq-b16
W17 Freq-b17
W18 Freq-b18
W19 Freq-b19
W20 Freq-b20
W21 Freq-b21
W22 Freq-b22
W23 Freq-b23
W24 Freq-b24
W25 Freq-b25
W26 Freq-b26
W27 Freq-b27