Datasheet

AD9850
–11–
REV. H
t
RH
CLK DELAY AFTER RESET RISING EDGE 3.5ns
t
RL
RESET FALLING EDGE AFTER CLK 3.5ns
t
RR
RECOVERY FROM RESET 2 CLK CYCLES
t
RS
MINIMUM RESET WIDTH 5 CLK CYCLES
t
OL
RESET OUTPUT LATENCY 13 CLK CYCLES
SYMBOL DEFINITION MINIMUM
RESULTS OF RESET:
– FREQUENCY/PHASE REGISTER SET TO 0
– ADDRESS POINTER RESET TO W0
– POWER-DOWN BIT RESET TO 0
– DATA INPUT REGISTER UNEFFECTED
t
RH
t
RL
t
RR
t
RS
t
OL
COS (0)
CLKIN
COS OUT
RESET
NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME
NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT
HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS NOT REQUIRED.
Figure 7. Master Reset Timing Sequence
XXXXX100
DATA (W0)
W
CLK
FQ
UD
CLKIN
INTERNAL CLOCKS DISABLED
DAC STROBE
Figure 8. Parallel Load Power-Down Sequence/Internal Operation
XXXXX000
DATA (W0)
W
CLK
FQ
UD
CLKIN
INTERNAL CLOCKS ENABLED
Figure 9. Parallel Load Power-Up Sequence/Internal Operation