Datasheet

AD9850
–10–
REV. H
t
DS
W0* W1 W2 W3 W4
t
DH
t
WH
t
WL
t
CF
VALID DATA
OLD FREQ (PHASE) NEW FREQ (PHASE)
*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD
AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK
DATA
W
CLK
CLKIN
COS OUT
t
DS
DATA SETUP TIME 3.5ns
t
DH
DATA HOLD TIME 3.5ns
t
WH
W CLK HIGH 3.5ns
t
WL
W CLK LOW 3.5ns
t
CD
CLK DELAY AFTER FQ_UD 3.5ns
t
FH
FQ UD HIGH 7.0ns
t
FL
FQ UD LOW 7.0ns
t
FD
FQ UD DELAY AFTER W CLK 7.0ns
t
CF
OUTPUT LATENCY FROM FQ UD
FREQUENCY CHANGE 18 CLOCK CYCLES
PHASE CHANGE 13 CLOCK CYCLES
SYMBOL DEFINITION MINIMUM
t
CD
t
FD
t
FH
t
FL
FQ UD
Figure 6. Parallel Load Frequency/Phase Update Timing Sequence
Table III. 8-Bit Parallel Load Data/Control Word Functional Assignment
Word Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0]
W0 Phase-b4 Phase-b3 Phase-b2 Phase-b1 Phase-b0 Power-Down Control Control
(MSB) (LSB)
W1 Freq-b31 Freq-b30 Freq-b29 Freq-b28 Freq-b27 Freq-b26 Freq-b25 Freq-b24
(MSB)
W2 Freq-b23 Freq-b22 Freq-b21 Freq-b20 Freq-b19 Freq-b18 Freq-b17 Freq-b16
W3 Freq-b15 Freq-b14 Freq-b13 Freq-b12 Freq-b11 Freq-b10 Freq-b9 Freq-b8
W4 Freq-b7 Freq-b6 Freq-b5 Freq-b4 Freq-b3 Freq-b2 Freq-b1 Freq-b0
(LSB)
Table II. Factory Reserved Internal Test Control Codes
Loading Format Factory Reserved Codes
Parallel 1) W0 = XXXXXX10
2) W0 = XXXXXX01
Serial 1) W32 = 1; W33 = 0
2) W32 = 0; W33 = 1
3) W32 = 1; W33 = 1