Datasheet

REV. A
–6–
AD9848/AD9849
TIMING SPECIFICATIONS
(C
L
= 20 pF, f
CLI
= 20 MHz (AD9848) or 30 MHz (AD9849), Serial Timing in Figures 3a and 3b,
unless otherwise noted.)
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI), AD9848
CLI Clock Period t
CLI
50 ns
CLI High/Low Pulsewidth t
ADC
25 ns
Delay From CLI to Internal Pixel Period Position t
CLIDLY
6ns
MASTER CLOCK (CLI), AD9849
CLI Clock Period t
CONV
33.33 ns
CLI High/Low Pulsewidth t
ADC
16.67 ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth t
CDM
410 Pixels
CLPOB Pulsewidth* t
COB
220 Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge (AD9848) t
S1
20 ns
SHP Rising Edge to SHD Rising Edge (AD9849) t
S1
13 ns
DATA OUTPUTS
Output Delay from Programmed Edge t
OD
6ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.