Datasheet

REV. A
AD9848/AD9849
–30–
CCD IMAGER
SIGNAL
OUT
13 14 20
29
RGH3 H4
H2H1 RG
AD9848/AD9849
CCDIN
H2 H1
17 18
H1 H2
Figure 22b. CCD Connections (4 H-Clock)
CLI
23
MASTER CLOCK
AD9848/AD9849
ASIC
Figure 23a. CLI Connection, DC-Coupled
CLI
23
MASTER CLOC
K
AD9848/AD9849
ASIC
LPF
1nF
Figure 23b. CLI Connection, AC-Coupled
Internal Mode Circuit Configuration
The AD9848/AD9849 may be used in Internal Mode using the
circuit configuration of Figure 24. Internal Mode uses the same
circuit as Figure 21, except that the horizontal pulses (CLPOB,
CLPDM, PBLK, and HBLK) are internally generated in the
AD9848/AD9849. These pins may be grounded when Internal
Mode is used. Only the HD and VD signals are required from
the ASIC.
HD/VD
INPUTS
2
44 3943
42
41
40
HD VD PBLK
HBLK
CLPDM
CLPOB
AD9848/AD9849
Figure 24. Internal Mode Circuit Configuration
TIMING EXAMPLES FOR DIFFERENT SEQUENCES
2
4
48
10
V
H
28
SEQUENCE 3
SEQUENCE 2
SEQUENCE 2
Figure 25. Typical CCD