Datasheet

REV. A
AD9848/AD9849
–11–
SYSTEM OVERVIEW
CCD
SERIAL
INTERFACE
DOUT
HD, VD
CLI
DIGITAL IMAGE
PROCESSING
ASIC
V-DRIVER
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
CCDIN
AD9848/AD9849
INTEGRATED
AFE+TD
Figure 1a. Typical Application (Internal Mode)
CCD
SERIAL
INTERFACE
DOUT
HD, VD
CLI
PBLK
HBLK
CLPDM
CLPOB
DIGITAL IMAGE
PROCESSING
ASIC
V-DRIVER
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
CCDIN
AD9848/AD9849
INTEGRATED
AFE+TD
Figure 1b. Typical Application (External Mode)
Figures 1a and 1b show the typical system application diagrams
for the AD9848/AD9849. The CCD output is processed by the
AD9848/AD9849’s AFE circuitry, which consists of a CDS,
PxGA, VGA, black level clamp, and A/D converter. The
digitized pixel information is sent to the digital image
processor chip, where all post-processing and compression
occurs. To operate the CCD, CCD timing parameters are
programmed into the AD9848/AD9849 from the image
processor, through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor, the
AD9848/AD9849 generates the high speed CCD clocks and all
internal AFE clocks. All AD9848/AD9849 clocks are
synchronized with VD and HD.
Figure 1a shows the AD9848/AD9849 used in Internal Mode, in
which all the horizontal pulses (CLPOB, CLPDM, PBLK,
and HBLK) are programmed and generated internally. Figure 1b
shows the AD9848/AD9849 operating in External Mode, in
which the horizontal pulses are supplied externally by the
image processor.
The H-drivers for H1–H4 and RG are included in the AD9848/
A
D9849, allowing these clocks to be directly connected to the
CCD. H-drive voltage of 5 V is supported in the AD9849.
Figure 2 shows the horizontal and vertical counter dimensions
for the AD9848/AD9849. All internal horizontal clocking is
programmed using these dimensions to specify line and
pixel locations.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
Figure 2. Vertical and Horizontal Counters