Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsAD9849AKSTZ

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

AD9848/AD9849

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

CCD Signal Processors with

Integrated Timing Driver

FUNCTIONAL BLOCK DIAGRAM

CLAMP

DOUT

CCDIN

PBLK

VRT

VRB

INTERNAL

REGISTERS

2dB TO 36dB

SYNC

GENERATOR

SDATASCK

CLPOB

10 OR 12

VGA

AD9848/AD9849

4ⴞ6dB

PRECISION

TIMING

CORE

ADC

VREF

CLAMP

INTERNAL

CLOCKS

PxGA

CDS

HORIZONTAL

DRIVERS

H1–H4

HD VD

CLI

CLPDM

FEATURES

AD9848: 10-Bit, 20 MHz Version

AD9849: 12-Bit, 30 MHz Version

Correlated Double Sampler (CDS)

–2 dB to +10 dB Pixel Gain Amplifier (

PxGA

)

2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)

10-Bit 20 MHz A/D Converter (AD9848)

12-Bit 30 MHz A/D Converter (AD9849)

Black Level Clamp with Variable Level Control

Complete On-Chip Timing Driver

Precision Timing

™

Core with 1 ns Resolution @ 20 MSPS

On-Chip 3 V Horizontal and RG Drivers (AD9848)

On-Chip 5 V Horizontal and RG Drivers (AD9849)

48-Lead LQFP Package

APPLICATIONS

Digital Still Cameras

PRODUCT DESCRIPTION

The AD9848 and AD9849 are highly integrated CCD signal

pro-

cessors for digital still camera applications. Both include a complete

analog front end with A/D conversion, combined with a program-

mable timing driver. The Precision Timing core allows adjustment

of high speed clocks with approximately 1 ns resolution.

The AD9848 is specified at pixel rates of 20 MHz, and the

AD9849 is specified at 30 MHz. The analog front end includes

black level clamping, CDS, PxGA, VGA, and a 10-bit or 12-bit A/D

converter. The timing driver provides the high speed CCD clock

drivers for RG and H1–H4. Operation is programmed using a

3-wire serial interface.

Packaged in a space saving 48-lead LQFP, the AD9848 and

AD9849 are specified over an operating temperature range of

–20°C to +85°C.

PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc.

Summary of content (32 pages)

PAGE 1
a CCD Signal Processors with Integrated Timing Driver AD9848/AD9849 FEATURES AD9848: 10-Bit, 20 MHz Version AD9849: 12-Bit, 30 MHz Version Correlated Double Sampler (CDS) –2 dB to +10 dB Pixel Gain Amplifier ( PxGA®) 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 20 MHz A/D Converter (AD9848) 12-Bit 30 MHz A/D Converter (AD9849) Black Level Clamp with Variable Level Control Complete On-Chip Timing Driver Precision Timing™ Core with 1 ns Resolution @ 20 MSPS On-Chip 3 V Horizontal and RG Drivers
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AD9848/AD9849–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter Min TEMPERATURE RANGE Operating Storage –20 –65 MAXIMUM CLOCK RATE AD9848 AD9849 20 30 POWER SUPPLY VOLTAGE, AD9848 Analog (AVDD1, 2, 3) Digital1 (DVDD1) H1–H4 Digital2 (DVDD2) RG Digital3 (DVDD3) D0–D11 Digital4 (DVDD4) All Other Digital Typ Max Unit +85 +150 °C °C MHz MHz 3.6 3.6 3.6 V V V V V 3.6 5.5 5.5 3.0 3.
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AD9848/AD9849 DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD1 = DVDD3, DVDD4 = 2.7 V, DVDD1, DVDD2 = 2.7 V (AD9848), DVDD1, DVDD2 = 5.25 V (AD9849), CL = 20 pF, unless otherwise noted.) Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance VIH VIL IIH IIL CIN 2.1 LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA VOH VOL 2.
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AD9848/AD9849 AD9848–ANALOG SPECIFICATIONS Parameter Min CDS Gain Allowable CCD Reset Transient* Max Input Range Before Saturation* Max CCD Black Pixel Amplitude* PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (32) Med Gain (0) Max Gain (31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (91) Max Gain (1023) Typ Max 0 500 Unit dB mV V p-p mV 1.
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AD9848/AD9849 AD9849–ANALOG SPECIFICATIONS Parameter Min CDS Gain Allowable CCD Reset Transient* Max Input Range Before Saturation* Max CCD Black Pixel Amplitude* PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (32) Med Gain (0) Max Gain (31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (91) Max Gain (1023) Typ Max 0 500 150 1.0 1.
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AD9848/AD9849 TIMING SPECIFICATIONS (CL = 20 pF, fCLI = 20 MHz (AD9848) or 30 MHz (AD9849), Serial Timing in Figures 3a and 3b, unless otherwise noted.) Parameter Symbol Min MASTER CLOCK (CLI), AD9848 CLI Clock Period CLI High/Low Pulsewidth Delay From CLI to Internal Pixel Period Position tCLI tADC tCLIDLY 50 25 MASTER CLOCK (CLI), AD9849 CLI Clock Period CLI High/Low Pulsewidth tCONV tADC 33.33 16.
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AD9848/AD9849 ABSOLUTE MAXIMUM RATINGS Parameter AVDD1, 2, 3 DVDD1, DVDD2 (AD9848) DVDD1, DVDD2 (AD9849) DVDD3, 4 Digital Outputs CLPOB, CLPDM, BLK CLI SCK, SL, SDATA VRT, VRB BYP1–3, CCDIN Junction Temperature Lead Temperature (10 sec) With Respect To Min Max Unit AVSS DVSS DVSS DVSS DVSS3 DVSS4 AVSS DVSS4 AVSS AVSS –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +3.9 +3.9 +5.5 +3.9 DVDD3 + 0.3 DVDD4 + 0.3 AVDD + 0.3 DVDD4 + 0.3 AVDD + 0.3 AVDD + 0.
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AD9848/AD9849 36 SL D2 1 35 REFT D3 2 D2 3 D3 4 34 REFB 33 CMLEVEL D4 5 DVSS3 6 32 AVSS3 31 AVDD3 BYP3 29 CCDIN SDI SCK CLPOB CLPDM HBLK PBLK AVSS3 31 AVDD3 30 29 BYP3 CCDIN AD9849 TOP VIEW (Not to Scale) D8 9 D9 10 28 BYP2 27 D10 11 26 BYP1 AVDD2 25 AVSS2 (MSB) D11 12 25 AVSS2 BYP2 AVDD1 CLI AVSS1 DVDD2 RG DVSS2 H4 H1 H3 13 14 15 16 17 18 19 20 21 22 23 24 AVDD1 CLI AVSS1 DVDD2 RG DVSS2 H4 H3 DVDD1 DVSS1 VD 32 13 14 15 16 17 18 19 20 21 22 23
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AD9848/AD9849 EQUIVALENT INPUT/OUTPUT CIRCUITS DVDD4 AVDD2 330⍀ R DVSS4 AVSS2 AVSS2 Circuit 1. CCDIN (Pin 29) Circuit 4. Digital Inputs (Pins 36–44) DVDD1 DATA AVDD1 330⍀ 25k⍀ ENABLE CLI OUTPUT 1.4V AVSS1 DVSS1 Circuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20) Circuit 2. CLI (Pin 23) DVDD4 DVDD3 DATA THREESTATE DOUT DVSS4 DVSS3 Circuit 3. Data Outputs D0–D11 (Pins 1–5, 8–12, 47–48) REV.
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AD9848/AD9849—Typical Performance Characteristics 0.50 0.5 0.25 0.25 0 0 –0.25 –0.25 –0.5 –0.50 0 200 400 600 800 0 1000 500 1000 1500 2000 2500 3000 3500 4000 TPC 3. AD9849 Typical DNL TPC 1. AD9848 Typical DNL 15 4 OUTPUT NOISE – LSB OUTPUT NOISE – LSB 3 2 10 5 1 0 0 0 200 400 600 VGA GAIN CODE – LSB 800 0 1000 TPC 2. AD9848 Output Noise vs. VGA Gain Setting 200 400 600 VGA GAIN CODE – LSB 800 1000 TPC 4. AD9849 Output Noise vs. VGA Gain Setting –10– REV.
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AD9848/AD9849 SYSTEM OVERVIEW V-DRIVER V1–V4, VSG1–VSG8, SUBCK V-DRIVER V1–V4, VSG1–VSG8, SUBCK H1–H4, RG DOUT H1–H4, RG CLPOB DOUT CCD CCD CCDIN AD9848/AD9849 INTEGRATED AFE+TD HD, VD DIGITAL IMAGE PROCESSING ASIC CCDIN AD9848/AD9849 INTEGRATED AFE+TD CLPDM PBLK DIGITAL IMAGE PROCESSING ASIC HBLK HD, VD CLI CLI SERIAL INTERFACE SERIAL INTERFACE Figure 1b. Typical Application (External Mode) Figure 1a.
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AD9848/AD9849 SERIAL INTERFACE TIMING SDATA A0 A1 A2 A3 t DS A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 XX XX t DH SCK t LS t LH SL SL UPDATED VD/HD UPDATED VD HD NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. 2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS. 3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED. 4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE, OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE. 5.
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AD9848/AD9849 clpdmscp3 register, the contents of Address 0x81 must be written first followed by the contents of Address 0x82. The register will be updated after the completion of the write to Register 0x82, either at the next SL rising edge or next VD/HD falling edge. Accessing a Double-Wide Register There are many double-wide registers in the AD9848/AD9849, for example, oprmode, clpdmtog1_0, and clpdmscp3, and so on.
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AD9848/AD9849 Address Bit Content Width Default Value Register Name Register Description CLPDM # Bits 146 64 65 [0] [0] 1 1 01 00 clpdmdir clpdmpol 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] 7A 7B 7C 7D 7E 7F 80 81 82 83 [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2 01 2C 00 35 00 01 3E 02 1
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AD9848/AD9849 Address Bit Content Width Default Value Register Name Register Description CLPOB # Bits 146 84 85 [0] [0] 1 1 01 00 clpobdir clpobpol 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2 01 0E 00 2B 00 01 2B 06 3
PAGE 16
AD9848/AD9849 Address Bit Content Width Default Value Register Name Register Description HBLK # Bits 147 A4 A5 [0] [0] 1 1 01 00 hblkdir hblkpol A6 [0] 1 01 hblkextmask A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] BB BC BD BE BF C0 C1 C2 C3 C4 [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2
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AD9848/AD9849 Address Bit Content Width Default Value Register Name Register Description PBLK # Bits 146 C5 C6 [0] [0] 1 1 01 00 pblkdir pblkpol C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] DB DC DD DE DF E0 E1 E2 E3 E4 [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 2 6 6 2 6 6 2 6 6 2 01 3D 00 2A 06 00 2A 06 3F 3
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AD9848/AD9849 Address Bit Content Width Default Value Register Name Register Description 8'h0 Serial Address: 8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]} AFE REGISTER BREAKDOWN oprmode [7:0] [1:0] 2'h0 2'h1 2'h2 2'h3 powerdown[1:0] [2] [3] [4] [5] [6] [7] ctlmode disblack test mode test mode test mode test mode test mode [5:0] [2:0] [3] [4] [5] Full Power Fast Recovery Reference Standby Total Shutdown Disable Black Loop Clamping (High Active) Test Mode—Should Be Set LOW Test Mode—Should Be Se
PAGE 19
AD9848/AD9849 POSITION P[12] P[0] P[24] P[36] P[48] = P[0] CLI ... tCLIDLY ... 1 PIXEL PERIOD NOTES 1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. 2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP). Figure 4.
PAGE 20
AD9848/AD9849 Table II. H1–H4, RG, SHP, SHD Timing Parameters Register Name Length Range Description POL POSLOC 1b 6b High/Low 0–47 Edge Location NEGLOC DRV 6b 3b 0–47 Edge Location 0–7 Current Steps Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion) Positive Edge Location for H1, H3, and RG Sample Location for SHP, SHD Negative Edge Location for H1, H3, and RG Drive Current for H1–H4 and RG Outputs (3.5 mA per Step) Table III.
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AD9848/AD9849 ... HD (2) CLPOB CLPDM (1) PBLK ... (3) CLAMP CLAMP NOTES PROGRAMMABLE SETTINGS: (1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW) (2) FIRST TOGGLE POSITION (3) SECOND TOGGLE POSITION Figure 9. Clamp and Preblank Pulse Placement ... HD ... (2) (1) BLANK HBLK BLANK NOTES PROGRAMMABLE SETTINGS: (1) FIRST TOGGLE POSITION = START OF BLANKING (2) SECOND TOGGLE POSITION = END OF BLANKING Figure 10. Horizontal Blanking (HBLK) Pulse Placement ... HD ...
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AD9848/AD9849 SINGLE FIELD (1 VD INTERVAL) SEQUENCE CHANGE OF POSITION #0 (V-COUNTER = 0) CLAMP AND PBLK SEQUENCE REGION 0 SEQUENCE CHANGE OF POSITION #1 CLAMP AND PBLK SEQUENCE REGION 1 SEQUENCE CHANGE OF POSITION #2 CLAMP AND PBLK SEQUENCE REGION 2 SEQUENCE CHANGE OF POSITION #3 CLAMP AND PBLK SEQUENCE REGION 3 UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS. Figure 12.
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AD9848/AD9849 POWER-UP PROCEDURE VDD (INPUT) CLI (INPUT) tPWR SERIAL WRITES 1V ... ... VD (OUTPUT) ODD FIELD EVEN FIELD 1H ... ... HD (OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, RG CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS UPDATED AT VD/HD EDGE Figure 14. Recommended Power-Up Sequence Recommended Power-Up Sequence DC Restore When the AD9848 and AD9849 are powered up, the following sequence is recommended (refer to Figure 14 for each step).
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AD9848/AD9849 0.1␮F 1.0␮F 1.0␮F REFB REFT CML AVDD 2 INTERNAL BIASING DC RESTORE SHP CCDIN SHD –2dB TO +10dB 0.1␮F DOUT PHASE 2V FULL SCALE OUTPUT DATA LATCH 10-/12-BIT ADC VGA PxGA CDS 10 10/12 DOUT OPTICAL BLACK CLAMP 8-BIT DAC VGA GAIN REGISTER INPUT OFFSET CLAMP 0.1␮F AD9848/AD9849 0dB TO 36dB CLPDM 0.1␮F 2.0V INTERNAL VREF 1.5V 0.1␮F 1.
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AD9848/AD9849 ODD FIELD FLD EVEN FIELD VD HD PxGA GAIN X REGISTER X 0 1 0 1 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 3 2 3 2 3 0 NOTES 1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE. 2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “2323” LINE. 3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER “0” (FLD = ODD) OR “2” (FLD = EVEN). Figure 16b.
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AD9848/AD9849 ODD FIELD FLD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 2 0 2 1 0 2 0 1 2 0 0 1 2 0 2 1 0 2 0 1 2 0 0 0 1 2 3 0 0 1 2 3 0 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “012012” LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “012012” AND “210210” LINES. 3. FLD STATUS IS IGNORED. Figure 16e.
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AD9848/AD9849 PxGA The PxGA provides separate gain adjustment for the individual color pixels. A programmable gain amplifier with four separate values, the PxGA has the capability to “multiplex” its gain value on a pixel-to-pixel basis (see Figure 17). This allows lower output color pixels to be gained up to match higher output color pixels. Also, the PxGA may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed.
PAGE 28
AD9848/AD9849 Variable Gain Amplifier The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface. Combined with 4 dB from the PxGA stage, the total gain range for the AD9848/AD9849 is 6 dB to 40 dB. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems (such as ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.
PAGE 29
AD9848/AD9849 0.1␮F 3V DIGITAL SUPPLY CLOCK INPUTS 6 SERIAL INTERFACE SDI SCK CLPOB CLPDM PBLK HBLK VD HD DVSS4 DVDD4 D0 (LSB) D1 3 1␮F 48 47 46 45 44 43 42 41 40 39 38 37 D2 1 D3 D4 D5 3V DRIVER SUPPLY 0.1␮F D6 DVSS3 DVDD3 D7 D8 36 PIN 1 IDENTIFIER 2 35 3 34 4 33 5 32 6 AD9849 7 TOP VIEW (Not to Scale) 8 31 30 29 9 28 D9 10 27 D10 11 (MSB) D11 26 12 25 1␮F REFB 0.1␮F CMLEVEL 0.1␮F AVSS3 3V ANALOG SUPPLY AVDD3 BYP3 CCDIN BYP2 0.
PAGE 30
AD9848/AD9849 Internal Mode Circuit Configuration The AD9848/AD9849 may be used in Internal Mode using the circuit configuration of Figure 24. Internal Mode uses the same circuit as Figure 21, except that the horizontal pulses (CLPOB, CLPDM, PBLK, and HBLK) are internally generated in the AD9848/AD9849. These pins may be grounded when Internal Mode is used. Only the HD and VD signals are required from the ASIC.
PAGE 31
AD9848/AD9849 Timing Examples (continued) CCDIN INVALID PIXELS VERT SHIFT DUMMY INVALID PIXELS VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 26. Sequence 1: Vertical Blanking EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY CCDIN OPTICAL BLACK VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 27. Sequence 2: Vertical Optical Black EFF. PIXELS CCDIN OPTICAL BLACK VERT SHIFT DUMMY OB EFFECTIVE PIXELS SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 28.
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AD9848/AD9849 OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) 1.60 MAX 0.75 0.60 0.45 PIN 1 INDICATOR 9.00 BSC 37 48 36 1 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 SEATING PLANE C02498–0–1/03(A) Dimensions shown in millimeters 7.00 BSC TOP VIEW (PINS DOWN) 7ⴗ 3.5ⴗ 0ⴗ 0.08 MAX COPLANARITY VIEW A 25 12 13 0.50 BSC VIEW A ROTATED 90ⴗ CCW 24 0.27 0.22 0.