Datasheet

REV. A
AD9847
–4–
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI)
CLI Clock Period t
CLI
25 ns
CLI High/Low Pulsewidth t
ADC
12.5 ns
Delay from CLI to Internal Pixel
Period Position t
CLIDLY
6ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth t
CDM
410Pixels
CLPOB Pulsewidth* t
COB
220 Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge t
S1
10 ns
DATA OUTPUTS
Output Delay from Programmed Edge t
OD
6ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
(C
L
to 29 pF, f
CLI
= 40 MHz, Serial Timing in Figures 3a and 3b, unless otherwise noted.)