Datasheet

AD9837
Data Sheet
Rev. A | Page 4 of 28
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
to T
MAX
Unit Description
t
1
62.5 ns min MCLK period (f
MCLK
= 16 MHz)
t
2
25 ns min MCLK high duration (f
MCLK
= 16 MHz)
t
3
25
ns min
MCLK low duration (f
MCLK
= 16 MHz)
t
4
25 ns min SCLK period
t
5
10 ns min SCLK high duration
t
6
10 ns min SCLK low duration
t
7
5 ns min FSYNC to SCLK falling edge setup time
t
8
10 ns min SCLK falling edge to FSYNC rising edge time
t
4
− 5 ns max
t
9
5 ns min Data setup time
t
10
3 ns min Data hold time
t
11
5 ns min SCLK high to FSYNC falling edge setup time
1
Guaranteed by design; not production tested.
Timing Diagrams
t
2
t
1
MCLK
t
3
09070-003
Figure 2. Master Clock
t
5
t
4
t
6
t
7
t
8
t
10
t
9
41
D5
1DD0
D1
D2D14
SCLK
FSYNC
SDATA
D15
t
11
09070-004
Figure 3. Serial Timing