Datasheet

AD9835 Data Sheet
Rev. A | Page 8 of 28
Pin No. Mnemonic Description
11, 12
PSEL0,
PSEL1
Phase Select Input. The AD9835 has four phase registers. These registers can be used to alter the value being input
to the COS ROM. The contents of the phase register are added to the phase accumulator output, the PSEL0 and
PSEL1 inputs selecting the phase register to be used. Alternatively, the phase register to be used can be selected
using the PSEL0 and PSEL1 bits. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising MCLK edge.
Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an uncertainty of
one MCLK cycle as to when control is transferred to the selected phase register. When the phase registers are
being controlled by the PSEL0 and PSEL1 bits, the pins should be tied to DGND.