50 MHz Direct Digital Synthesizer, Waveform Generator AD9835 Data Sheet FEATURES GENERAL DESCRIPTION 5 V power supply 50 MHz speed On-chip COS lookup table On-chip, 10-bit DAC Serial loading Power-down option Temperature range: −40°C to +85°C 200 mW power consumption 16-Lead TSSOP The AD9835 is a numerically-controlled oscillator employing a phase accumulator, a COS lookup table, and a 10-bit digitalto-analog converter integrated on a single CMOS chip.
AD9835 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Latency......................................................................................... 17 Applications....................................................................................... 1 Flowcharts ................................................................................... 17 General Description ............................................
Data Sheet AD9835 SPECIFICATIONS VDD = +5 V ± 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; RSET = 3.9 kΩ; RLOAD = 300 Ω for IOUT, unless otherwise noted. Also, see Figure 2. Table 1.
AD9835 Data Sheet RSET 3.9kΩ 10nF ON-BOARD REFERENCE 12 SIN ROM REFIN FS ADJUST FULL-SCALE CONTROL 10-BIT DAC COMP AVDD 10nF IOUT 300Ω AD9835 Figure 2. Test Circuit Rev.
Data Sheet AD9835 TIMING CHARACTERISTICS VDD = +5 V ± 5%; AGND = DGND = 0 V, unless otherwise noted. Table 2.
AD9835 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = +25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND AVDD to DVDD AGND to DGND Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to DVDD + 0.
Data Sheet AD9835 FS ADJUST 1 16 COMP REFIN 2 15 AVDD REFOUT 3 14 IOUT DVDD 4 AD9835 13 AGND DGND 5 TOP VIEW (Not to Scale) 12 PSEL0 MCLK 6 11 PSEL1 SCLK 7 10 FSELECT SDATA 8 9 FSYNC 09630-006 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description ANALOG SIGNAL AND REFERENCE Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND.
AD9835 Pin No. 11, 12 Mnemonic PSEL0, PSEL1 Data Sheet Description Phase Select Input. The AD9835 has four phase registers. These registers can be used to alter the value being input to the COS ROM. The contents of the phase register are added to the phase accumulator output, the PSEL0 and PSEL1 inputs selecting the phase register to be used. Alternatively, the phase register to be used can be selected using the PSEL0 and PSEL1 bits.
Data Sheet AD9835 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AVDD = DVDD = +5V –4 SFDR [±2MHz] (dB) –10 CL = 82pF –6 –8 –20 –30 –40 CL = 150pF 0 2 4 6 8 10 12 14 16 OUTPUT FREQUENCY (MHz) –60 10 –20 TA = +25°C AVDD = DVDD = +5V 20 15 10 –40 50MHz –50 30MHz –60 10MHz –70 30 20 40 50 MCLK FREQUENCY (MHz) –80 0.044 09630-008 0 10 Figure 8. Typical Current Consumption vs. MCLK Frequency 0.084 0.124 0.164 0.
AD9835 70 Data Sheet AVDD = DVDD = +5V 10MHz 60 30MHz 50MHz 10dB/DIV SNR (dB) 50 40 30 0.164 0.204 0.244 0.284 0.324 0.364 fOUT/fMCLK 0Hz START RBW 1kHz 10dB/DIV 10dB/DIV 0Hz START RBW 1kHz 09630-014 VBW 3kHz 25MHz STOP ST 50 SEC VBW 3kHz 25MHz STOP ST 50 SEC Figure 17. fMCLK = 50 MHz, fOUT = 9.1 MHz. Frequency Word = 2E978D50 10dB/DIV 10dB/DIV Figure 14. fMCLK = 50 MHz, fOUT = 2.1 MHz.
AD9835 VBW 3kHz 25MHz STOP ST 50 SEC 0Hz START RBW 1kHz 09630-019 0Hz START RBW 1kHz Figure 19. fMCLK = 50 MHz, fOUT = 13.1 MHz. Frequency Word = 43126E98 VBW 3kHz 25MHz STOP ST 50 SEC 09630-020 10dB/DIV 10dB/DIV Data Sheet Figure 20. fMCLK = 50 MHz, fOUT = 16.5 MHz. Frequency Word = 547AE148 Rev.
AD9835 Data Sheet TERMINOLOGY Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
Data Sheet AD9835 THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a(t) = sin (ωt). However, these are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of ω = 2 πf.
AD9835 Data Sheet CIRCUIT DESCRIPTION The AD9835 provides an exciting level of integration for the RF communications system designer. The AD9835 combines the numerical controlled oscillator (NCO), COS lookup table, frequency and phase modulators, and a digital-to- analog converter on a single integrated circuit. The internal circuitry of the AD9835 consists of three main sections. These are • • • Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit PHASE registers.
Data Sheet AD9835 FUNCTIONAL DESCRIPTION SERIAL INTERFACE The AD9835 has a serial interface, with 16 bits loaded during each write cycle. SCLK, SDATA, and FSYNC are used to load the word into the AD9835. continuous, or alternatively, the SCLK can idle high or low between write operations.
AD9835 Data Sheet Table 8. Control Registers Register FREQ0 REG Size 32 bits FREQ1 REG 32 bits PHASE0 REG 12 bits PHASE1 REG 12 bits PHASE2 REG 12 bits PHASE3 REG 12 bits Description Frequency Register 0. This defines the output frequency, when FSELECT = 0, as a fraction of the MCLK frequency. Frequency Register 1. This defines the output frequency, when FSELECT = 1, as a fraction of the MCLK frequency. Phase Offset Register 0.
Data Sheet AD9835 Table 12. Setting SYNC and SELSRC D15 1 1 D14 0 D13 SYNC D12 SELSRC D11 X1 D10 X1 D9 X1 D8 X1 D7 X1 D6 X1 D5 X1 D4 X1 D3 X1 D2 X1 D1 X1 D0 X1 D9 X1 D8 X1 D7 X1 D6 X1 D5 X1 D4 X1 D3 X1 D2 X1 D1 X1 D0 X1 X = don’t care. Table 13. Power-Down, Resetting and Clearing the AD9835 D15 1 1 D14 1 D13 SLEEP D12 RESET D11 CLR D10 X1 X = don’t care.
AD9835 Data Sheet DATA WRITE FREG[0] = fOUT0/fMCLK × 232 FREG[1] = fOUT1/fMCLK × 232 PHASEREG [3:0] = DELTA PHASE[0, 1, 2, 3] SELECT DATA SOURCES SET FSELECT SET PSEL0, PSEL1 INITIALIZATION WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = 1) DAC OUTPUT VOUT = VREFIN × 6.25 × ROUT/RSET × (1 + SIN(2π(FREG × fMCLK × t/232 + PHASEREG/212))) CHANGE PHASE? YES NO NO CHANGE fOUT? YES CHANGE fOUT? CHANGE PHASEREG? YES NO CHANGE PSEL0, PSEL1 09630-024 NO YES Figure 22.
Data Sheet AD9835 DATA WRITE DEFERRED TRANSFER WRITE WRITE 8 BITS TO DEFER REGISTER DIRECT TRANSFER WRITE WRITE PRESENT 8 BITS AND 8 BITS IN DEFER REGISTER TO DATA REGISTER CHANGE 16 BITS WRITE ANOTHER WORD TO THIS YES REGISTER? YES NO CHANGE 8 BITS ONLY 09630-026 NO WRITE A WORD TO ANOTHER REGISTER Figure 24. Data Writes SELECT DATA SOURCES NO YES SELSRC = 0 SET PINS SET FSELECT SET PSEL0 SET PSEL1 SELSRC = 1 FREQUENCY/PHASE REGISTER WRITE SET FSELECT SET PSEL0 SET PSEL1 Figure 25.
AD9835 Data Sheet APPLICATIONS INFORMATION The AD9835 has four phase registers; this enables the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator. The presence of four shift registers eases the interaction needed between the DSP and the AD9835. The AD9835 is also suitable for signal generator applications.
Data Sheet AD9835 Figure 27 shows the serial interface between the AD9835 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting bit MSTR in the SPCR to 1 and, this provides a serial clock on SCK while the MOSI output drives the serial data line SDATA. Since the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7).
AD9835 Data Sheet EVALUATION BOARD SYSTEM DEMONSTRATION PLATFORM The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin® BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. Note that the SDP board is sold separately from the AD9835 evaluation board.
Data Sheet AD9835 EVALUATION BOARD SCHEMATICS AND LAYOUT Figure 32. AD9835 Schematic, Part A Rev.
AD9835 Data Sheet 09630-034 Figure 33. AD9835 Schematic, Part B Rev.
AD9835 09630-036 Data Sheet 09630-037 Figure 34. Component Side View Layer 1 09630-038 Figure 35. Component Side View Silkscreen Figure 36. Component Side View Layer 2, Solder Side Rev.
AD9835 Data Sheet ORDERING INFORMATION BILL OF MATERIALS Table 14. Reference Designator C1, C3, C5, C6, C111, C12, C131 Description 0.1 μF, ±10%, 50 V, X7R, ceramic capacitor Manufacturer Murata Part Number GRM188R71H104KA93D C7 C2, C4 C8,C9 C10 CLK 1 , FSEL1, IOUT, PSEL11, REFIN, PSEL01 FSYNC, IOUT_, MCLK , SCLK, SDATA G2 J1 J2, J3 LK3, LK5, LK6 LK1 R71, R81, R91 R121 R14 R15 R17,R18 R1, R21, R3, R41, R61, R5, R111, R10,R162 R13 U4 U1 U5 Y2 0.
Data Sheet AD9835 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 37.
AD9835 Data Sheet NOTES ©1998–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09630-0-9/11(A) Rev.
