Datasheet

AD9834
Rev. C | Page 6 of 36
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
to T
MAX
Unit Test Conditions/Comments
t
1
20/13.33 ns min MCLK period: 50 MHz/75 MHz
t
2
8/6 ns min MCLK high duration: 50 MHz/75 MHz
t
3
8/6 ns min MCLK low duration: 50 MHz/75 MHz
t
4
25 ns min SCLK period
t
5
10 ns min SCLK high duration
t
6
10 ns min SCLK low duration
t
7
5 ns min FSYNC-to-SCLK falling edge setup time
t
8 MIN
10 ns min FSYNC-to-SCLK hold time
t
8 MAX
t
4
− 5 ns max
t
9
5 ns min Data setup time
t
10
3 ns min Data hold time
t
11
8 ns min FSELECT, PSELECT setup time before MCLK rising edge
t
11A
8 ns min FSELECT, PSELECT setup time after MCLK rising edge
t
12
5 ns min SCLK high to FSYNC falling edge setup time
1
Guaranteed by design, not production tested.
Timing Diagrams
MCLK
t
1
t
3
t
2
02705-003
Figure 3. Master Clock
FSELECT,
PSELECT
VALID DATA VALID DATA VALID DATA
MCLK
t
11A
t
11
02705-004
Figure 4. Control Timing
D0
SCLK
FSYNC
SDATA
D15 D14 D2 D1 D15 D14
t
12
t
7
t
6
t
8
t
5
t
4
t
9
t
10
02705-005
Figure 5. Serial Timing