Datasheet

Data Sheet AD9832
Rev. E | Page 17 of 28
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
INITIALIZATION
WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = 1)
DAC OUTPUT
V
OUT
= V
REFIN
× 6.25 × R
OUT
/R
SET
× (1 + SIN(2π(FREG × f
MCLK
× t/2
32
+ PHASEREG/2
12
)))
CHANGE PHASE?
NO
CHANGE f
OUT
?
CHANGE f
OUT
?
YES
NO
YES
NO
YES
CHANGE FSELECT
CHANGE PHASEREG?
NO
YES
CHANGE PSEL0, PSEL1
DATA WRITE
FREG[0] = f
OUT0
/ f
MCLK
× 2
32
FREG[1] = f
OUT1
/
f
MCLK
× 2
32
PHASEREG [3:0] = DELTA PHASE[0, 1, 2, 3]
09090-024
Figure 24. Flowchart for the AD9832 Initialization and Operation
INITIALIZATION
CONTROL REGISTER WRITE
SET SLEEP
RESET = 1
CLR = 1
SET SYNC AND/OR SELSRC TO 1
YES
NO
CONTROL REGISTER WRITE
SYNC = 1
AND/OR
SELSRC = 1
SET PINS OR FREQUENCY/PHASE REGISTER WRITE
SET FSELECT, PSEL0 AND PSEL1
CONTROL REGISTER WRITE
SLEEP = 0
RESET = 0
CLR = 0
WRITE INITIAL DATA
FREG[0] = f
OUT0
/ f
MCLK
× 2
32
FREG[1] = f
OUT1
/ f
MCLK
× 2
32
PHASEREG[3:0] = DELTA PHASE[0, 1, 2, 3]
09090-025
Figure 25. Initialization
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