Datasheet

–2–
AD9830–SPECIFICATIONS
1
Parameter AD9830A Units Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate (f
MAX
) 50 MSPS max
I
OUT
Full Scale 20 mA max
Output Compliance 1 V max
DC Accuracy
Integral Nonlinearity ±1 LSB typ
Differential Nonlinearity ±0.5 LSB typ
DDS SPECIFICATIONS
2
Dynamic Specifications
Signal-to-Noise Ratio 50 dB min f
MCLK
= f
MAX
, f
OUT
= 2 MHz
Total Harmonic Distortion –53 dBc max f
MCLK
= f
MAX
, f
OUT
= 2 MHz
Spurious Free Dynamic Range (SFDR)
3
f
MCLK
= 6.25 MHz, f
OUT
= 2.11 MHz
Narrow Band
(±50 kHz) –72 dBc min
(±200 kHz) –68 dBc min
Wide Band (±2 MHz) –50 dBc min
Clock Feedthrough –55 dBc typ
Wake Up Time 1 ms typ
Power-Down Option Yes
VOLTAGE REFERENCE
Internal Reference @ +25°C 1.21 Volts typ
T
MIN
to T
MAX
1.21 ± 7% Volts min/max
REFIN Input Impedance 10 MΩ typ
Reference TC 100 ppm/°C typ
REFOUT Impedance 300 Ω typ
LOGIC INPUTS
V
INH
, Input High Voltage V
DD
–0.9 V min
V
INL
, Input Low Voltage 0.9 V max
I
INH
, Input Current 10 µA max
C
IN
, Input Capacitance 10 pF max
POWER SUPPLIES f
OUT
= 2 MHz
AVDD 4.75/5.25 V min/V max
DVDD 4.75/5.25 V min/V max
I
AA
25 mA max
I
DD
6 + 0.5/MHz mA typ
I
AA
+ I
DD
4
60 mA max
Low Power Sleep Mode
5
0.25 mA typ 1 MΩ Resistor Tied Between
1 mA max REFOUT and AGND
(V
DD
= +5 V 6 5%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
; REFIN = REFOUT;
R
SET
= 1 kV; R
LOAD
= 51 V for IOUT and IOUT unless otherwise noted)
NOTES
1
Operating temperature range is as follows: A Version: –40°C to +85°C.
2
All dynamic specifications are measured using IOUT. 100% production tested.
3
f
MCLK
= 6.25 MHz, Frequency Word = 5671C71C HEX, f
OUT
= 2.11 MHz.
4
Measured with the digital inputs static and equal to 0 V or DVDD.
5
The Low Power Sleep Mode current is 2 mA typically when a 1 MΩ resistor is
not tied from REFOUT to AGND.
The AD9830 is tested with a capacitive load of 50 pF. The part can be operated
with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 10 MHz output signal will be attenuated by 3 dB when the
load capacitance equals 250 pF.
Specifications subject to change without notice.
FULL-SCALE
CONTROL
10-BIT
DAC
SIN
ROM
ON-BOARD
REFERENCE
12
REFOUT REFIN FS
ADJUST
COMP
IOUT
IOUT
51Ω
50pF
51Ω
50pF
AVDD
R
SET
1kΩ
10nF
10nF
Figure 1. Test Circuit with Which Specifications Are
Tested
REV. B