Datasheet

AD9826
–9–
t
AD
t
AD
t
C2ADR
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL n
PIXEL (n+1)
PIXEL (n+2)
t
C1
t
C2C1
t
C2
t
C2ADF
t
ADC2
t
ADCLK
t
ADCLK
HIGH
BYTE
LOW
BYTE
CH1(n–2)
t
C1C2
CH2(n–2) CH1(n–1) CH2(n–1)
LOW
BYTE
LOW
BYTE
LOW
BYTE
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
t
PRA
CH1(n)
Figure 3. 2-Channel CDS Mode Timing
t
AD
t
ADCLK
t
ADCLK
t
C2ADR
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL n
PIXEL
(n+1)
t
C2
t
C2ADF
t
ADC2
HIGH
BYTE
LOW
BYTE
LOW
BYTE
LOW
BYTE
LOW
BYTE
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
HIGH
BYTE
CH1(n–2)
CH2(n–2)
CH1(n–1) CH2(n–1)
CH1(n)
Figure 4. 2-Channel SHA Mode Timing
REV. B