Datasheet

AD9826
–10–
t
AD
PIXEL n (R,G,B)
t
C2
t
ADCLK
t
ADCLK
t
C2ADR
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
R (n–1)
t
C2AD
t
ADC2
HIGH
BYTE
LOW
BYTE
t
OD
t
PRA
HB LB HB HB HB HB HBLB LB
LB
LB LB
R (n–2)
G (n–2)
G (n–2)
B (n–2) B (n–2) R (n–1)
G (n–1)
G (n–1) B (n–1)
B (n–1) R (n) R (n) G (n)
G (n)
PIXEL (n+1)
Figure 5. 3-Channel SHA Mode Timing
HIGH BYTE LOW BYTE LOW BYTE LOW BYTEHIGH BYTE HIGH BYTE
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL n
t
AD
t
C2ADR
t
OD
t
PRB
PIXEL (n–4) PIXEL (n–4) PIXEL (n–3) PIXEL (n–3) PIXEL (n–2) PIXEL (n–2)
t
C2ADF
t
ADCLK
t
C2
t
ADCLK
t
ADCLK
NOTE
IN 1-CHANNEL SHA MODE, THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”
Figure 6. 1-Channel SHA Mode Timing
REV. B