Datasheet

AD9822
Rev. B | Page 9 of 20
PIXEL N (R, G, B) PIXEL (N + 1)
t
AD
t
C2
t
C2ADF
t
ADC2
t
C2ADR
t
ADCLK
t
ADCLK
t
OD
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
R (N– 2) G (N– 2) G (N– 2) B (N– 2) B (N– 2) R (N– 1) R (N– 1) G (N– 1) G (N– 1) B (N– 1) B (N– 1) R (N) R (N) G (N) G (N)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
t
ADC1
t
AD
t
C1
CDSCLK1
PIXEL
(N + 2)
00623-004
t
C2C1
t
C1C2
t
PRA
Figure 3. 3-Channel CDS Mode Timing
t
AD
PIXEL N
t
AD
ANALOG
INPUTS
t
OD
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
t
C2
PIXEL
(N – 4)
PIXEL
(N – 4)
PIXEL
(N – 3)
PIXEL
(N – 3)
PIXEL
(N – 2)
PIXEL
(N – 2)
t
C1C2
t
C1
CDSCLK1
t
ADC1
HIGH BYTE LOW BYTE LOW BYTEHIGH BYTE LOW BYTEHIGH BYTE
PIXEL (N + 1) PIXEL (N + 2)
t
C2ADR
00623-005
t
C2C1
t
PRB
t
C2ADF
t
ADCLK
t
ADCLK
Figure 4. 1-Channel CDS Mode Timing