Datasheet

AD9822
Rev. B | Page 15 of 20
CIRCUIT OPERATION
ANALOG INPUTS—CDS MODE
Figure 10 shows the analog input configuration for the CDS
mode of operation. Figure 11 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage representing the difference between the two
sampled levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1 is
high, S4 closes and the internal bias voltage is connected to the
analog input. The bias voltage charges the external 0.1 µF input
capacitor, level-shifting the CCD signal into the AD9822’s input
common-mode range. The time constant of the input clamp is
determined by the internal 5 kΩ resistance and the external
0.1 µF input capacitance.
AD9822
S1
S2
2pF
S3
2pF
CML
CML
AVDD
4V
S4
5kΩ
1.7kΩ
VINR
OFFSET
C
IN
0.1µF
CCD SIGNA
L
0.1µF1µF
+
3V
2.2kΩ
6.9kΩ
INPUT CLAMP LEVEL
IS SELECTED IN THE
CONFIGURATION
REGISTER.
00362-011
Figure 10. CDS Mode Input Configuration (All Three Channels are Identical)
CDSCLK1
CDSCLK2
Q3
(INTERNAL)
S1, S4 CLOSED S1, S4 CLOSED
S2 CLOSED S2 CLOSED
S3 CLOSED S3 CLOSED
S3 OPEN
S2 OPEN
S1, S4 OPEN
00623-012
Figure 11. CDS Mode Internal Switch Timing
EXTERNAL INPUT COUPLING CAPACITORS
The recommended value for the input coupling capacitors is
0.1 µF. While it is possible to use a smaller capacitor, this larger
value is chosen for several reasons:
• Signal Attenuation: The input coupling capacitor creates a
capacitive divider with a CMOS integrated circuit’s input
capacitance, attenuating the CCD signal level. CIN should be
large relative to the IC’s 10 pF input capacitance in order to
minimize this effect.
• Linearity: Some of the input capacitance of a CMOS IC is
junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, the
attenuation of the CCD signal varies nonlinearly with signal
level. This degrades the system linearity performance.
• Sampling Errors: The internal 2 pF sample capacitors have a
“memory” of the previously sampled pixel. There is a charge
redistribution error between CIN and the internal sample
capacitors for larger pixel-to-pixel voltage swings. As the
value of CIN is reduced, the resulting error in the sampled
voltage increases. With a CIN value of 0.1 µF, the charge
redistribution error is less than 1 LSB for a full-scale, pixel-to-
pixel voltage swing.