Datasheet

AD9822
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
3-Channel Pixel Rate t
PRA
67 ns
1-Channel Pixel Rate t
PRB
80 ns
ADCCLK Pulse Width t
ADCLK
30 ns
CDSCLK1 Pulse Width t
C1
10 ns
CDSCLK2 Pulse Width t
C2
10 ns
CDSCLK1 Falling to CDSCLK2 Rising t
C1C2
0 ns
ADCCLK Falling to CDSCLK2 Rising t
ADC2
0 ns
CDSCLK2 Rising to ADCCLK Rising t
C2ADR
0 ns
CDSCLK2 Falling to ADCCLK Falling t
C2ADF
30 40 ns
CDSCLK2 Falling to CDSCLK1 Rising t
C2C1
30 40 ns
ADCCLK Falling to CDSCLK1 Rising t
ADC1
0 ns
Aperture Delay for CDS Clocks t
AD
2 ns
SERIAL INTERFACE
Maximum SCLK Frequency f
SCLK
10 MHz
SLOAD to SCLK Setup Time t
LS
10 ns
SCLK to SLOAD Hold Time t
LH
10 ns
SDATA to SCLK Rising Setup Time t
DS
10 ns
SCLK Rising to SDATA Hold Time t
DH
10 ns
SCLK Falling to SDATA Valid t
RDV
10 ns
DATA OUTPUT
Output Delay t
OD
8 ns
Three-State to Data Valid t
DV
10 ns
Output Enable High to Three-State t
HZ
10 ns
Latency (Pipeline Delay) 3 (Fixed) Cycles