Datasheet

REV. 0
AD9806
–9–
SERIAL INTERFACE SPECIFICATIONS
MODES2
1
SDATA
SELECT
DAC2
DAC1
PGA
MODES
A0
0
A1
1
A2
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
e0 e1 d0 d1 c0 c1 b0 b1 a0 a1
CLAMP
LEVEL
POWER-DOWN
MODES
CLOCK
MODES
OUTPUT
MODES
OPERATION
MODES
f0 f1 f2 f3 f4 f5 f6 f7 f8 f9
PGA GAIN LEVEL SELECTION
g0 g1 g2 g3 g4 g5 g6 g7
h0 h1 h2 h3 h4 h5 h6 h7
m0 0* j0
DAC1 INPUT
DAC2 INPUT
OPERATION AND
POWER-DOWN MODES
SHIFT REGISTER
F-REG
f0–f9
E-REG
e0–e1
D-REG
(d) POWER-DOWN MODES
d0–d1
C-REG
c0–c1
B-REG
b0–b1
A-REG
(a) OPERATION MODES
a0–a1
(b) OUTPUT MODES (c) CLOCK MODES (e) CLAMP LEVEL (f) PGA GAIN
M-REG
m0
J-REG
j0
H-REG
h0–h7
G-REG
(g) DAC1 INPUT
g0–g7
(h) DAC2 INPUT (j) EVEN-ODD OFFSET
CORRECTION
(m) DAC1 AND DAC2
POWER-DOWN
SELECT
*NOTE: MODES2 REGISTER BIT D1 MUST BE SET TO ZERO
DON'T
CARE
111
1
1
1
10
0
0
00
Figure 7. AD9806 Internal Register Map
RISING EDGE
TRIGGERED
t
DH
t
LS
t
LH
REGISTER LOADED ON
RISING EDGE
RNW
A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
SDATA
SCK
SL
t
DS
Figure 8. Serial WRITE Operation
SDATA
RNW
A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 XX XX
DUMMY BITS
IGNORED
SCK
SL
Figure 9. 16-Bit Serial WRITE Operation