Datasheet

AD9786
Rev. B | Page 27 of 56
CLOCK/DATA TIMING
Table 26. Data Port Synchronization
DCLKEXT
0x02, Bit 3
MODSYNC
0x05, Bit 3
DCLKCRC
0x02, Bit 2 Mode Function
1 0 X DATACLK Master Channel data rate clock output
1 1 X Modulator Master
Modulator synchronization
DATACLK output
0 0 0 External Sync Mode
DATACLK inactive, DACCLK
synchronous with external data
0 0 1 DATACLK Slave
DATACLK input, data rate clock,
data recovery on
0 1 0 Low Setup/Hold
DATACLK input, input data
synchronous with DATACLK
0 1 1 Modulator Slave
Input modulator synchronizer
DATACLK input
Two-Port Data Input Mode (DATACLK Master)
With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same frequency.
Note that DACCLK refers to the differential clock inputs applied
at Pin 5 and Pin 6. As Figure 44 and Figure 45 show, there is a
constant delay between the edges of DACCLK and DATACLK.
The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be
latched into the AD9786 upon either the rising or falling edge
of DACCLK. With DCLKPOL = 0, the data is latched in upon
the falling edge of DACCLK, as shown in Figure 44. With
DCLKPOL = 1, as shown in Figure 45, data is latched in upon
the rising edge of DACCLK. The setup and hold times are
always with respect to the latching edge of DACCLK.
03152-044
DACCLK
IN
DATACLK
OUT
DATA
t
12
t
D
= 6ns TYP
t
H
= 2.9ns MIN t
S
= –0.5ns MIN
Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0
03152-045
DACCLK
IN
DATACLK
OUT
DATA
t
D
= 5.5ns TYP
t
H
= 2.9ns MIN t
S
= –0.5ns MIN
Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1
With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the digital
inputs of the AD9786 upon every other rising edge of DACCLK,
as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as
shown in Figure 47, the latching edge of DACCLK is the rising
edge that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is
the rising edge of DACCLK that occurs just before the rising edge
of DATACLK. The setup and hold time values are identical to
those in Figure 44 and Figure 45.
Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 46 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.
With the interpolation set to 4× or 8×, the DACCLK input
runs at 4× or 8× the speed of the DATACLK output. The data
is latched in upon a rising edge of DACCLK, similar to the
2× interpolation mode.
However, the latching edge is every fourth edge in 4× inter-
polation mode and every eighth edge in the 8× interpolation
mode. Similar to operation in the 2× interpolation mode, with
DCLKPOL = 0, the latching edge of DACCLK is the rising edge
that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, the latching edge of DACCLK is the rising
edge that occurs just before the rising edge of DATACLK.
The setup and hold time values are identical to those in 1×
and 2× interpolation.