Datasheet

AD9786
Rev. B | Page 24 of 56
Table 16.
DCLKCRC(05) Bit Direction Default Description
DATAADJ[3:0] [7:4] I 0000
DATACLK offset (twos complement representation)
0111: +7
:
0000: 0
:
1000: −8
MODSYNC 3 I 00 0: Channel data rate clock synchronizer mode
1: State machine clock synchronizer mode
f
S
/8 f
S
/4 f
S
/2
000 1 1 1
001 +1/√2 0 –1
010 0 –1 1
011 –1/√2 0 –1
100 –1 +1 +1
101 –1/√2 0 –1
110 0 –1 +1
MODADJ[2:0] [2:0] I 000
111 +1/√2 0 –1
Modulator coefficient offset
Table 17.
VERSION(0D) Bit Direction Default Description
VERSION[3:0] [3:0] O Hardware version identifier
Table 18.
CALMEMCK(OE) Bit Direction Default Description
CALMEM [5:4] O 00 Calibration memory
00: Uncalibrated
01: Self-calibration
10: Factory calibration
11: User input
CALCKDIV[2:0] [2:0] I 00 Calibration clock divide ratio from channel data rate
000: /32
001: /64
:
110: /2048
111: /4096
Table 19.
MEMRDWR(OF) Bit Direction Default Description
CALSTAT 7 O 0 0: Self-calibration cycle not complete
1: Self-calibration cycle complete
CALEN 6 I 0 1: Self-calibration in progress
XFERSTAT 5 O 0 0: Factory memory transfer not complete
1: Factory memory transfer complete
XFEREN 4 I 0 1: Factory memory transfer in progress
SMEMWR 3 I 0 1: Write static memory data from external port
SMEMRD 2 I 0 1: Read static memory to external port
FMEMRD 1 I 0 1: Read factory memory data to external port
UNCAL 0 I 0 1: Use uncalibrated