Datasheet

AD9786
Rev. B | Page 23 of 56
Table 14.
DATA(02) Bit Direction Default Description
DATAFMT 7 I 0 0: Twos complement data format
1: Unsigned binary input data format
ONEPORT 6 I 0 0: I and Q input data onto Port 1 and Port 2, respectively
1: I and Q input data interleaved onto Port 1
DCLKSTR 5 I 0 0: DATACLK pin, 12 mA drive strength
1: DATACLK pin, 24 mA drive strength
DCLKPOL 4 I 0 0: Input data latched on DATACLK/DACCLK rising edge (dependent on mode)
1: Input data latched on DATACLK/DACCLK falling edge (dependent on mode)
DCLKEXT 3 I 0 0: DATACLK pin inputs channel data rate or modulator synchronizer clock
1: DATACLK pin outputs channel data rate or modulator synchronizer clock
DCLKCRC 2 I 0 0: With DATACLK pin as input, DATACLK clock recovery off
1: With DATACLK pin as input, DATACLK clock recovery on
IQPOL 1 I 0
0: In one-port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data
into Q channel
1: In one-port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data
into Q channel
GRAYDIN 0 I 0 0: Gray decoder off
1: Gray decoder on
Table 15.
MODULATE(03) Bit Direction Default Description
MODDUAL
0x03[5]
CHANNEL
0x03[7]
0 0 I channel processing routed to DAC
0 1 Q channel processing routed to DAC
1 0 Modulator real output routed to DAC
CHANNEL 7 I 0
1 1 Modulator imaginary output routed to DAC
HILBERT 6 I 0 1: With MODDUAL on, Hilbert transform on
MODDUAL 5 I 0 0: Modulator uses a single channel
1: Modulator uses both I and Q channels
SIDEBAND 4 I 0 0: With MODDUAL on, upper sideband rejected
1: With MODDUAL on, lower sideband rejected
MOD[1:0] [3:2] I 00 00: No modulation
01: f
S
/2 modulation
10: f
S
/4 modulation
11: f
S
/8 modulation